Nanoxplore synthesis does not works when using abc9 flow

[samhanic]

Version

Yosys 0.45 (git sha1 9ed031d, g++ 13.3.0 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

Create any design.v file containing combinational logic.
Run command: yosys -p "read_verilog design.v; synth_nanoxplore -abc9 ; write_json design.json"

Expected Behavior

Design synthetises and outputs the design netlist in design.json file.

Actual Behavior

Yosys errors out at ABC9 step:

2.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
ERROR: Module 'NX_LUT' with (* abc9_lut *) has no specify entries.