Wildcard package imports (`import pkg::*`) fail to resolve typedefs

[warricklo]

Version

Yosys 0.64+341 (git sha1 cc9692c, Release, GNU /usr/bin/c++ 12.2.0)

On which OS did it happen?

WSL (Debian, kernel 6.6.87.2-1)

Reproduction steps

test_pkg.sv

package test_pkg;

  localparam int XLEN = 32;

  typedef logic [7:0] byte_t;

endpackage

test1.sv

import test_pkg::*;

module test (
  input logic [XLEN-1:0] x,
  input byte_t a
);

  byte_t b;

endmodule

test2.sv

import test_pkg::*;

module test (
  input logic [XLEN-1:0] x,
  input test_pkg::byte_t a
);

  byte_t b;

endmodule

# Test 1
yosys -p "read_verilog -sv test_pkg.sv test1.sv"

# Test 2
yosys -p "read_verilog -sv test_pkg.sv test2.sv"

Expected behaviour

Importing typedefs from packages should parse and resolve correctly. The wildcard import at the top should make byte_t available in both the port declaration and module body, just like XLEN.

Actual behaviour

Imported typedefs don't work, neither in the port declaration nor in the module body. However localparams and enum values work as expected.

Yosys output:

-- Running command `read_verilog -sv test_pkg.sv test1.sv' --

1. Executing Verilog-2005 frontend: test_pkg.sv
Parsing SystemVerilog input from `test_pkg.sv' to AST representation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: test1.sv
Parsing SystemVerilog input from `test1.sv' to AST representation.
test1.sv:5: ERROR: syntax error, unexpected TOK_ID, expecting ')' or ',' or '='

-- Running command `read_verilog -sv test_pkg.sv test2.sv' --

1. Executing Verilog-2005 frontend: test_pkg.sv
Parsing SystemVerilog input from `test_pkg.sv' to AST representation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: test2.sv
Parsing SystemVerilog input from `test2.sv' to AST representation.
test2.sv:8: ERROR: syntax error, unexpected ';', expecting '(' or '['

In both cases Yosys will exit with code 1.

Works as expected

Using fully qualified names (test_pkg::byte_t) works. The following test elaborates successfully.

test3.sv

import test_pkg::*;

module test (
  input logic [XLEN-1:0] x,
  input test_pkg::byte_t a
);

  test_pkg::byte_t b;

endmodule

yosys> read_verilog -sv test_pkg.sv

# ...

yosys> read_verilog -sv test3.sv

2. Executing Verilog-2005 frontend: test3.sv
Parsing SystemVerilog input from `test3.sv' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.