Assertion in hierarchy when elaborating parameterized generate instances due to non-unique name

[jojomon7892-creator]

Version

Yosys 0.66+183 (git sha1 b285b72, GNU /usr/bin/c++ 13.3.0)

On which OS did this happen?

Linux

Reproduction Steps

In directory with CanonicalNBitBinaryAdd.v and CanonialNBitBinaryMultiply.v run the the command

yosys -p "read_verilog -sv ./*.v; hierarchy -top CanonicalNBitBinaryMultiply -chparam AWIDTH 2 -chparam BWIDTH 2 -chparam RWIDTH 4 -chparam COUNTGATES 0 -purge_lib; stat"

MultiplyError.zip

Expected Behavior

The design elaborates successfully. I have a divide that uses similar parameterized modules that does elaborate successfully. I used the command bellow to run the divide.

yosys -p "read_verilog -sv ./*.v; hierarchy -top CanonicalNBitBinaryDivide -chparam AWIDTH 2 -chparam BWIDTH 2 -chparam RWIDTH 4 -chparam COUNTGATES 0 -purge_lib; stat"

DivideExpected.zip

Actual Behavior

I expect the multiply to elaborate but it fails with the error below every time. I have tried changing my run commands but no permutation has had an effect.
ERROR: Assert `modules_.count(module->name) == 0' failed in /home/jojomon/Palace/KAOS/PbitOpt/NewYosys/yosys/kernel/rtlil.cc:1229.

[KrystalDelusion]

I believe this is happening when instantiating the second module named add, though I'm not entirely sure why it is a problem for the multiply and not the divide. If you change the default params in the multiplier (or have a wrapper module which uses the desired params) and drop the chparam option then it works fine. Otherwise you could try do an array of instances with add[abits-1:0], but you might need to restructure the signals to work with it.