Feature Description
As slang/sv-elab are now bundled with yosys , I am moving this question here.
povik/sv-elab#296
To summarize, what is the proper way to instantiate a vhdl generic entity in a SystemVerilog module.
The vhdl entity is read using the ghdl plugin.
Things seem to work seamlessly with read_verilog command, but not with the slang_read command.
As if the elaboration of the vhdl is done differently.
Feature Description
As slang/sv-elab are now bundled with yosys , I am moving this question here.
povik/sv-elab#296
To summarize, what is the proper way to instantiate a vhdl generic entity in a SystemVerilog module.
The vhdl entity is read using the ghdl plugin.
Things seem to work seamlessly with
read_verilogcommand, but not with theslang_readcommand.As if the elaboration of the vhdl is done differently.