Moved 100 MHz fallback

acidanthera · Sep 10, 2024 · 9656a0c · 9656a0c
1 parent 29be882
commit 9656a0c
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Showing 2 changed files with 7 additions and 19 deletions.
diff --git a/Library/OcAppleKernelLib/CpuidPatches.c b/Library/OcAppleKernelLib/CpuidPatches.c
@@ -1646,34 +1646,21 @@ PatchProvideCurrentCpuInfo (
   // Perform TSC and FSB calculations. This is traditionally done in tsc.c in XNU.
   //
   // For AMD Processors
-  if ((CpuInfo->Family == 0xF) && ((CpuInfo->ExtFamily == 0x8) || (CpuInfo->ExtFamily == 0xA))) {
+  if ((CpuInfo->Family == 0xF) && ((CpuInfo->ExtFamily == 0x8) || (CpuInfo->ExtFamily == 0xA) || (CpuInfo->ExtFamily == 0xB))) {
     DEBUG ((DEBUG_INFO, "OCAK: Setting FSB and TSC for Family 0x%x and ExtFamily 0x%x\n", (UINT16)CpuInfo->Family, (UINT16)CpuInfo->ExtFamily));
-    busFreqValue    = CpuInfo->FSBFrequency;
-    busFCvtt2nValue = DivU64x64Remainder ((1000000000ULL << 32), busFreqValue, NULL);
-    busFCvtn2tValue = DivU64x64Remainder ((1000000000ULL << 32), busFCvtt2nValue, NULL);
-
-    tscFreqValue    = CpuInfo->CPUFrequency;
-    tscFCvtt2nValue = DivU64x64Remainder ((1000000000ULL << 32), tscFreqValue, NULL);
-    tscFCvtn2tValue = DivU64x64Remainder ((1000000000ULL << 32), tscFCvtt2nValue, NULL);
-
-  } else if (CpuInfo->ExtFamily == 0xB) {
-
-    // Family 1Ah has different handling: no divisor (DID)
     busFreqValue = CpuInfo->FSBFrequency;
 
     // Handle case where FSBFrequency is zero, providing a fallback
-    if (busFreqValue == 0) {
+    if (busFreqValue == 0)
+    {
       busFreqValue = 100000000; // Assume 100 MHz FSB as fallback
       DEBUG ((DEBUG_WARN, "OCAK: FSBFrequency is zero, using fallback value: 100 MHz\n"));
     }
 
-    // Calculate bus FCvtt2n and FCvtn2t values
     busFCvtt2nValue = DivU64x64Remainder ((1000000000ULL << 32), busFreqValue, NULL);
     busFCvtn2tValue = DivU64x64Remainder ((1000000000ULL << 32), busFCvtt2nValue, NULL);
 
-    // Get TSC frequency and calculate TSC FCvtt2n and FCvtn2t values
     tscFreqValue = CpuInfo->CPUFrequency;
-
     tscFCvtt2nValue = DivU64x64Remainder ((1000000000ULL << 32), tscFreqValue, NULL);
     tscFCvtn2tValue = DivU64x64Remainder ((1000000000ULL << 32), tscFCvtt2nValue, NULL);
   }

diff --git a/Library/OcCpuLib/OcCpuLib.c b/Library/OcCpuLib/OcCpuLib.c
@@ -692,8 +692,9 @@ ScanAmdProcessor (
     switch (Cpu->ExtFamily) {
       case AMD_CPU_EXT_FAMILY_1AH:
         if (Cpu->CPUFrequencyFromVMT == 0) {
-          CofVid = AsmReadMsr64(K10_PSTATE_STATUS);
-          CoreFrequencyID = (UINT16)BitFieldRead64(CofVid, 0, 11);  // 12-bit field for FID
+          CofVid          = AsmReadMsr64(K10_PSTATE_STATUS);
+          CoreFrequencyID = (UINT16)BitFieldRead64(CofVid, 0, 11); // 12-bit field for FID
+
           // On AMD Family 1Ah and later, if the Frequency ID (FID) exceeds 0x0f,
           // the core frequency is scaled by a factor of 5. This scaling behavior
           // is based on Linux kernel logic for handling higher frequency multipliers
@@ -810,7 +811,7 @@ ScanAmdProcessor (
       // Sometimes incorrect hypervisor configuration will lead to dividing by zero.
       //
       if (MaxBusRatio == 0) {
-        Cpu->FSBFrequency = 100000000; // Default to 100 MHz like Intel part.
+        Cpu->FSBFrequency = 100000000; // 100 MHz like Intel part.
       } else {
         // Special handling for Family 1Ah
         if (Cpu->ExtFamily == AMD_CPU_EXT_FAMILY_1AH) {