Ax7203_board

example/AX7203_ARTIX7/fpga/Makefile

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+# Targets
+TARGETS:=
+
+# Subdirectories
+SUBDIRS = fpga
+SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
+
+# Rules
+.PHONY: all
+all: $(SUBDIRS) $(TARGETS)
+
+.PHONY: $(SUBDIRS)
+$(SUBDIRS):
+	cd $@ && $(MAKE)
+
+.PHONY: $(SUBDIRS_CLEAN)
+$(SUBDIRS_CLEAN):
+	cd $(@:.clean=) && $(MAKE) clean
+
+.PHONY: clean
+clean: $(SUBDIRS_CLEAN)
+	-rm -rf $(TARGETS)
+
+program:
+	#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit

example/AX7203_ARTIX7/fpga/README.md

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+# Verilog Ethernet ARTIX Example Design
+
+## Introduction
+
+This example design targets the Digilent Nexys Video FPGA board.
+
+The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
+will echo back any packets received.  The design will also respond correctly
+to ARP requests.  
+
+*  FPGA: XC7A200TFBG484-2
+*  PHY:  KSZ9031RNX
+
+## How to build
+
+Run make to build.  Ensure that the Xilinx Vivado toolchain components are
+in PATH.  
+
+## How to test
+
+Run make program to program the Nexys Video board with the Digilent command
+line tools.  Then run
+
+    netcat -u 192.168.1.128 1234
+
+to open a UDP connection to port 1234.  Any text entered into netcat will be
+echoed back after pressing enter.
+
+It is also possible to use hping to test the design by running
+
+    sudo hping3 192.168.1.128 -2 -p 1234 -d 1024

example/AX7203_ARTIX7/fpga/common/vivado.mk

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+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+
+SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+else
+  XDC_FILES_REL = $(PROJECT).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi

example/AX7203_ARTIX7/fpga/eth.xdc

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+# Ethernet constraints
+
+# IDELAY on RGMII from PHY chip
+set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}]
+
+
+

example/AX7203_ARTIX7/fpga/fpga.xdc

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+# XDC constraints for the Digilent Nexys Video board
+# part: xc7a200tfbg484-2
+
+# General configuration
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
+
+# differential clock
+set_property -dict {PACKAGE_PIN R4 IOSTANDARD DIFF_SSTL15} [get_ports clk_p]
+set_property -dict {PACKAGE_PIN T4 IOSTANDARD DIFF_SSTL15} [get_ports clk_n]
+create_clock -period 5.000 -name clk [get_ports clk_p]
+
+# Reset button
+set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS15} [get_ports reset_n]
+
+set_false_path -from [get_ports reset_n]
+set_input_delay 0.000 [get_ports reset_n]
+
+
+# Gigabit Ethernet RGMII PHY
+set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
+set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
+set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
+set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
+set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
+set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports phy_rx_ctl]
+
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports phy_tx_clk]
+set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports {phy_txd[0]}]
+set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports {phy_txd[1]}]
+set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports {phy_txd[2]}]
+set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports {phy_txd[3]}]
+set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports phy_tx_ctl]
+set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
+create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk]
+
+#set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_mdio]
+#set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_mdc]
+#set_false_path -to [get_ports {phy_mdio phy_mdc}]
+#set_output_delay 0.000 [get_ports {phy_mdio phy_mdc}]
+#set_false_path -from [get_ports phy_mdio]
+#set_input_delay 0.000 [get_ports phy_mdio]
+#set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25} [get_ports phy_int_n]
+#set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25} [get_ports phy_pme_n]
+#set_false_path -from [get_ports {phy_int_n phy_pme_n}]
+#set_input_delay 0 [get_ports {phy_int_n phy_pme_n}]
+
+set_false_path -to [get_ports phy_reset_n]
+set_output_delay 0.000 [get_ports phy_reset_n]
+
+
+#new
+

example/AX7203_ARTIX7/fpga/fpga/Makefile

@@ -0,0 +1,59 @@
+
+# FPGA settings
+FPGA_PART = xc7a200t-fbg484-2
+FPGA_TOP = fpga
+FPGA_ARCH = artix7
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += lib/eth/rtl/iddr.v
+SYN_FILES += lib/eth/rtl/oddr.v
+SYN_FILES += lib/eth/rtl/ssio_ddr_in.v
+SYN_FILES += lib/eth/rtl/ssio_ddr_out.v
+SYN_FILES += lib/eth/rtl/rgmii_phy_if.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii_fifo.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g.v
+SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
+SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
+SYN_FILES += lib/eth/rtl/lfsr.v
+SYN_FILES += lib/eth/rtl/eth_axis_rx.v
+SYN_FILES += lib/eth/rtl/eth_axis_tx.v
+SYN_FILES += lib/eth/rtl/udp_complete.v
+SYN_FILES += lib/eth/rtl/udp_checksum_gen.v
+SYN_FILES += lib/eth/rtl/udp.v
+SYN_FILES += lib/eth/rtl/udp_ip_rx.v
+SYN_FILES += lib/eth/rtl/udp_ip_tx.v
+SYN_FILES += lib/eth/rtl/ip_complete.v
+SYN_FILES += lib/eth/rtl/ip.v
+SYN_FILES += lib/eth/rtl/ip_eth_rx.v
+SYN_FILES += lib/eth/rtl/ip_eth_tx.v
+SYN_FILES += lib/eth/rtl/ip_arb_mux.v
+SYN_FILES += lib/eth/rtl/arp.v
+SYN_FILES += lib/eth/rtl/arp_cache.v
+SYN_FILES += lib/eth/rtl/arp_eth_rx.v
+SYN_FILES += lib/eth/rtl/arp_eth_tx.v
+SYN_FILES += lib/eth/rtl/eth_arb_mux.v
+SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
+SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
+SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+XDC_FILES += eth.xdc
+XDC_FILES += lib/eth/syn/vivado/rgmii_phy_if.tcl
+XDC_FILES += lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl
+XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
+XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
+XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	djtgcfg prog -d NexysVideo --index 0 --file $(FPGA_TOP).bit
+

example/AX7203_ARTIX7/fpga/fpga/create_project.tcl

@@ -0,0 +1,4 @@
+create_project -force -part xc7a200t-fbg484-2 fpga
+add_files -fileset sources_1 defines.v ../rtl/fpga.v ../rtl/fpga_core.v ../rtl/sync_signal.v ../lib/eth/rtl/iddr.v ../lib/eth/rtl/oddr.v ../lib/eth/rtl/ssio_ddr_in.v ../lib/eth/rtl/ssio_ddr_out.v ../lib/eth/rtl/rgmii_phy_if.v ../lib/eth/rtl/eth_mac_1g_rgmii_fifo.v ../lib/eth/rtl/eth_mac_1g_rgmii.v ../lib/eth/rtl/eth_mac_1g.v ../lib/eth/rtl/axis_gmii_rx.v ../lib/eth/rtl/axis_gmii_tx.v ../lib/eth/rtl/lfsr.v ../lib/eth/rtl/eth_axis_rx.v ../lib/eth/rtl/eth_axis_tx.v ../lib/eth/rtl/udp_complete.v ../lib/eth/rtl/udp_checksum_gen.v ../lib/eth/rtl/udp.v ../lib/eth/rtl/udp_ip_rx.v ../lib/eth/rtl/udp_ip_tx.v ../lib/eth/rtl/ip_complete.v ../lib/eth/rtl/ip.v ../lib/eth/rtl/ip_eth_rx.v ../lib/eth/rtl/ip_eth_tx.v ../lib/eth/rtl/ip_arb_mux.v ../lib/eth/rtl/arp.v ../lib/eth/rtl/arp_cache.v ../lib/eth/rtl/arp_eth_rx.v ../lib/eth/rtl/arp_eth_tx.v ../lib/eth/rtl/eth_arb_mux.v ../lib/eth/lib/axis/rtl/arbiter.v ../lib/eth/lib/axis/rtl/priority_encoder.v ../lib/eth/lib/axis/rtl/axis_fifo.v ../lib/eth/lib/axis/rtl/axis_async_fifo.v ../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v ../lib/eth/lib/axis/rtl/sync_reset.v
+set_property top fpga [current_fileset]
+add_files -fileset constrs_1 ../fpga.xdc ../eth.xdc ../lib/eth/syn/vivado/rgmii_phy_if.tcl ../lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl ../lib/eth/syn/vivado/eth_mac_fifo.tcl ../lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl ../lib/eth/lib/axis/syn/vivado/sync_reset.tcl

example/AX7203_ARTIX7/fpga/fpga/fpga.bit

@@ -0,0 +1 @@
+fpga.runs/impl_1/fpga.bit

example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/project.wpc

@@ -0,0 +1,4 @@
+version:1
+57656254616c6b5472616e736d697373696f6e417474656d70746564:1
+6d6f64655f636f756e7465727c42617463684d6f6465:4
+eof:

example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/synthesis.wdf

@@ -0,0 +1,48 @@
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