This repository contains the Nios V Example designs based on different Altera FPGA development kits.
The following table contains the list of Acronyms that the user may come across in the design details
| Acronym | Expansion |
|---|---|
| DMA | Direct Memory Access |
| OCM | On-Chip Memory |
| PIO | Parallel I/O |
| RTOS | Real Time Operating System |
| ECC | Error-Correcting Code |
| TCM | Tightly Coupled Memory |
| GHRD | Golden Hardware Reference Design |
| SSS | Simple Socket Server |
| CI | Custom Instrcution |
| CRC | Cyclic Redundancy Check |
There are three variants of the NiosV core:
a. Nios V/m core - Microcontroller- Balanced (For interrupt driven baremetal and RTOS code)
b. Nios V/g core - General-Purpose Processor- High Performance (For interrupt driven baremetal and RTOS code)
c. Nios V/c core - Compact Microcontroller- Smallest (For non-interrupt driven baremetal code)
Example Designs using Nios V as the core based on Agilex™ 5 FPGA E-Series 065B Premium Development Kit
Development Kit product page- https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-premium.html
The following table contains the list of the designs on Agilex 5 FPGA E-Series 065B Premium Development Kit
| No # | Design Name Prefix (Nios V core) | Design Name Suffix (Functions) | Description |
|---|---|---|---|
| 1 | Nios V/m | Nios V/m DMA OCM Design | This design demonstrates the transaction between the Nios® V processor with DMA and OCM core Design details |
| 2 | Nios V/g | Nios V/g TinyML LiteRT | This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor Design details |
| 3 | Nios V/g | Nios V/g Helloworld Design | Nios® V/g Processor-based Helloworld example design Design details |
| 4 | Nios V/g | Nios V/g OCM Memory Tese Design | Nios® V/g Processor-based OCM memory test example design Design details |
| 5 | Nios V/c | Nios V/c Helloworld OCM Memory test Design | Nios® V/c Processor-based Helloworld and OCM memory test example design Design details |
| 6 | Nios V/m | Nios V/m Baseline Golden Hardware Reference Design (GHRD) | This design demonstrates the baseline Golden Hardware Reference Design (GHRD) for a Nios V/m processor with basic bare minimum peripherals required for any application execution Design details |