This repository contains the Nios V Example designs based on different Altera Agilex™ FPGA Development Kits.
The following table contains the list of Acronyms that the user may come across in the design details
| Acronym | Expansion |
|---|---|
| DMA | Direct Memory Access |
| OCM | On-Chip Memory |
| PIO | Parallel I/O |
| RTOS | Real Time Operating System |
| ECC | Error-Correcting Code |
| TCM | Tightly Coupled Memory |
| SSS | Simple Socket Server |
| CI | Custom Instrcution |
| CRC | Cyclic Redundancy Check |
There are three variants of the NiosV core:
a. Nios V/m core - Microcontroller- Balanced (For interrupt driven baremetal and RTOS code)
b. Nios V/g core - General-Purpose Processor- High Performance (For interrupt driven baremetal and RTOS code)
c. Nios V/c core - Compact Microcontroller- Smallest (For non-interrupt driven baremetal code)
| Development Kit OPN | Development Kit Name | Development Kit product page URL |
|---|---|---|
| agf014ea-dev-devkit | Agilex™ 7 FPGA F-Series Development Kit (P-Tile and E-Tile) | https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agf014.html |
The following table contains the list of the designs on Agilex™ 7 FPGA F-Series Development Kit (P-Tile and E-Tile)
| No # | Design Name Prefix (Nios V core) | Design Name Suffix (Functions) | Description |
|---|---|---|---|
| 1 | Nios V/g | Nios V/g TinyML LiteRT | This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor Design details |
| Development Kit OPN | Development Kit Name | Development Kit product page URL |
|---|---|---|
| agf014eb-si-devkit | Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile) | https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/si-agf014.html |
The following table contains the list of the designs on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)
| No # | Design Name Prefix (Nios V core) | Design Name Suffix (Functions) | Description |
|---|---|---|---|
| 1 | Nios V/g | Nios V/g FPU Design | Nios V/g Processor-based design example with Floating Point Unit (FPU) on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile) Design details |
Refer to the documents in the following link for More information on the Nios V Processor core - https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/nios-v-support.html