This repository contains the Nios V Example designs based on different Altera FPGA development kits.
The following table contains the list of Acronyms that the user may come across in the design details
| Acronym | Expansion |
|---|---|
| DMA | Direct Memory Access |
| OCM | On-Chip Memory |
| PIO | Parallel I/O |
| RTOS | Real Time Operating System |
| ECC | Error-Correcting Code |
| TCM | Tightly Coupled Memory |
| GHRD | Golden Hardware Reference Design |
| SSS | Simple Socket Server |
| CI | Custom Instrcution |
| CRC | Cyclic Redundancy Check |
There are three variants of the NiosV core:
a. Nios V/m core - Microcontroller- Balanced (For interrupt driven baremetal and RTOS code)
b. Nios V/g core - General-Purpose Processor- High Performance (For interrupt driven baremetal and RTOS code)
c. Nios V/c core - Compact Microcontroller- Smallest (For non-interrupt driven baremetal code)
Example Designs using Nios V as the core based on Max® 10 FPGA 10M50 Evaluation Kit
Development Kit product page- https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/max/10m50-evaluation-kit.html
The following table contains the list of the designs on Max® 10 FPGA 10M50 Evaluation Kit
| No # | Design Name Prefix (Nios V core) | Design Name Suffix (Functions) | Description |
|---|---|---|---|
| 1 | Nios V/g | Nios V/g TinyML LiteRT | This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor Design details |
Refer to the documents in the following link for More information on the Nios V Processor core - https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/nios-v-support.html