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msp430: fix BR instruction behavior and register-indirect @Rn disassembly #65

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merged 2 commits into from
May 6, 2024
Merged

msp430: fix BR instruction behavior and register-indirect @Rn disassembly #65

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fbdb48d
msp430: fix BR instruction
jovanbulck May 3, 2024
3afeca2
msp430: fix disassembly register-indirect @Rn mode
jovanbulck May 3, 2024
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4 changes: 2 additions & 2 deletions angr_platforms/msp430/instrs_msp430.py
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Original file line number Diff line number Diff line change
Expand Up @@ -330,7 +330,7 @@ def decorate_reg(self, reg_name, reg_mode, imm):
reg_str = "%d(%s)" % (imm, reg_name)
# Indirect mode; fetch address in register; store is a write there.
elif reg_mode == ArchMSP430.Mode.INDIRECT_REGISTER_MODE:
reg_str = "@%s" % reg_str
reg_str = "@%s" % reg_name
# Indirect Autoincrement mode. Increment the register by the type size, then access it
elif reg_mode == ArchMSP430.Mode.INDIRECT_AUTOINCREMENT_MODE:
reg_str = "@%s+" % reg_name
Expand Down Expand Up @@ -648,7 +648,7 @@ def compute_result(self, src, dst):
self.jump(None, newpc, jumpkind=JumpKind.Ret)
else:
# If we're setting PC, but not from SP+, it's a BR instead
self.jump(None, self.constant(self.addr, REGISTER_TYPE))
self.jump(None, src)
return src

def negative(self, src, dst, ret):
Expand Down