arm64_addrenv: Add support for 4 level MMU translations #13560
Merged
+113
−52
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Summary
The original code made the incorrect assumption that the amount of
translation levels is 3, but this is incorrect. The amount of levels is 4
and the amount of levels that are utilized / in use is set dynamically
from the amount of VA bits in use.
Impact
Support for 4 level translations in ARM64 address environments
Testing
QEMU + iMX93 with kernel mode