feat: add basic loongarch64 support

.gitignore

@@ -6,3 +6,4 @@
 actual.out
 qemu.log
 rusty-tags.vi
+.idea

Makefile

@@ -103,8 +103,13 @@ else ifeq ($(ARCH), aarch64)
   ACCEL ?= n
   PLATFORM_NAME ?= aarch64-qemu-virt
   TARGET := aarch64-unknown-none-softfloat
+else ifeq ($(ARCH), loongarch64)
+  ACCEL ?= n
+  PLATFORM_NAME ?= loongarch64-qemu-virt
+  TARGET := loongarch64-unknown-none
+  BUS := pci
 else
-  $(error "ARCH" must be one of "x86_64", "riscv64", or "aarch64")
+  $(error "ARCH" must be one of "x86_64", "riscv64", "aarch64" or "loongarch64")
 endif
 
 export AX_ARCH=$(ARCH)
@@ -118,6 +123,9 @@ export AX_GW=$(GW)
 
 # Binutils
 CROSS_COMPILE ?= $(ARCH)-linux-musl-
+ifeq ($(ARCH), loongarch64)
+	CROSS_COMPILE := $(ARCH)-unknown-linux-gnu-
+endif
 CC := $(CROSS_COMPILE)gcc
 AR := $(CROSS_COMPILE)ar
 RANLIB := $(CROSS_COMPILE)ranlib

apps/exception/expect_debug_loongarch64.out

@@ -0,0 +1,19 @@
+smp = 1
+build_mode = release
+log_level = debug
+
+Primary CPU 0 started,
+Found physcial memory regions:
+ .text (READ | EXECUTE | RESERVED)
+ .rodata (READ | RESERVED)
+ .data .tdata .tbss .percpu (READ | WRITE | RESERVED)
+ .percpu (READ | WRITE | RESERVED)
+ boot stack (READ | WRITE | RESERVED)
+ .bss (READ | WRITE | RESERVED)
+ free memory (READ | WRITE | FREE)
+Initialize platform devices...
+Primary CPU 0 init OK.
+Running exception tests...
+Exception(Breakpoint) @ 0x[0-9a-f]\{16\}
+Exception tests run OK!
+Shutting down...

apps/exception/src/main.rs

@@ -15,6 +15,8 @@ fn raise_break_exception() {
         asm!("brk #0");
         #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
         asm!("ebreak");
+        #[cfg(any(target_arch = "loongarch64"))]
+        asm!("break 0");
     }
 }
 

crates/kernel_guard/src/arch/loongarch64.rs

@@ -0,0 +1,18 @@
+use core::arch::asm;
+
+/// Bit 2: Supervisor Interrupt Enable
+const IE_BIT: usize = 1 << 2;
+
+#[inline]
+pub fn local_irq_save_and_disable() -> usize {
+    let mut flags: usize = 0;
+    // clear the `IE` bit, and return the old CSR
+    unsafe { asm!("csrxchg {}, {}, 0x0", inout(reg) flags, in(reg) IE_BIT) };
+    flags & IE_BIT
+}
+
+#[inline]
+pub fn local_irq_restore(mut flags: usize) {
+    // restore the `IE` bit
+    unsafe { asm!("csrxchg {}, {}, 0x0", inout(reg) flags, in(reg) IE_BIT) };
+}

crates/kernel_guard/src/arch/mod.rs

@@ -10,5 +10,8 @@ cfg_if::cfg_if! {
     } else if #[cfg(target_arch = "aarch64")] {
         mod aarch64;
         pub use self::aarch64::*;
+    } else if #[cfg(target_arch = "loongarch64")] {
+        mod loongarch64;
+        pub use self::loongarch64::*;
     }
 }

crates/page_table/src/arch/loongarch64.rs

@@ -0,0 +1,16 @@
+//! LoongArch64 specific page table structures.
+
+use crate::{PageTable64, PagingMetaData};
+
+use page_table_entry::loongarch64::LA64PTE;
+/// Metadata of LoongArch64 page tables.
+#[derive(Copy, Clone, Debug)]
+pub struct LA64MetaData;
+
+impl const PagingMetaData for LA64MetaData {
+    const LEVELS: usize = 4;
+    const PA_MAX_BITS: usize = 48;
+    const VA_MAX_BITS: usize = 48;
+}
+
+pub type LA64PageTable<I> = PageTable64<LA64MetaData, LA64PTE, I>;

crates/page_table/src/arch/mod.rs

@@ -6,3 +6,6 @@ pub mod riscv;
 
 #[cfg(any(target_arch = "aarch64", doc))]
 pub mod aarch64;
+
+#[cfg(any(target_arch = "loongarch64", doc))]
+pub mod loongarch64;