x86_64 virtio:get irqnum support for x86_64 virtio dev

modules/axconfig/src/platform/pc-x86.toml

@@ -21,6 +21,7 @@ mmio-regions = [
     ["0xfec0_0000", "0x1000"],      # IO APIC
     ["0xfed0_0000", "0x1000"],      # HPET
     ["0xfee0_0000", "0x1000"],      # Local APIC
+    ["0xe_0000", "0x2_0000"],       # ACPI
 ]
 # VirtIO MMIO regions with format (`base_paddr`, `size`).
 virtio-mmio-regions = []

modules/axdriver/src/bus/pci.rs

@@ -84,7 +84,14 @@ fn config_pci_device(
 
 impl AllDevices {
     pub(crate) fn probe_bus_devices(&mut self) {
-        let base_vaddr = phys_to_virt(axconfig::PCI_ECAM_BASE.into());
+        cfg_if::cfg_if! {
+            if #[cfg(all(target_arch = "x86_64",feature = "virtio"))] {
+                let pci_ecam_base = axhal::pci::get_ecam_address().unwrap();
+            } else {
+                let pci_ecam_base = axconfig::PCI_ECAM_BASE.into();
+            }
+        }
+        let base_vaddr = phys_to_virt(pci_ecam_base);
         let mut root = unsafe { PciRoot::new(base_vaddr.as_mut_ptr(), Cam::Ecam) };
 
         // PCI 32-bit MMIO space

modules/axhal/Cargo.toml

@@ -50,6 +50,8 @@ x86 = "0.52"
 x86_64 = "0.14"
 x2apic = "0.4"
 raw-cpuid = "11.0"
+acpi = "4.1.1"
+aml = "0.16.4"
 
 [target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
 riscv = "0.10"

modules/axhal/src/arch/x86_64/mod.rs

@@ -2,7 +2,7 @@ mod context;
 mod gdt;
 mod idt;
 
-#[cfg(target_os = "none")]
+// #[cfg(target_os = "none")]
 mod trap;
 
 use core::arch::asm;
@@ -14,6 +14,7 @@ use x86_64::instructions::interrupts;
 pub use self::context::{ExtendedState, FxsaveArea, TaskContext, TrapFrame};
 pub use self::gdt::GdtStruct;
 pub use self::idt::IdtStruct;
+pub use self::trap::{IRQ_VECTOR_END, IRQ_VECTOR_START};
 pub use x86_64::structures::tss::TaskStateSegment;
 
 /// Allows the current CPU to respond to interrupts.

modules/axhal/src/arch/x86_64/trap.rs

@@ -4,8 +4,10 @@ use super::context::TrapFrame;
 
 core::arch::global_asm!(include_str!("trap.S"));
 
-const IRQ_VECTOR_START: u8 = 0x20;
-const IRQ_VECTOR_END: u8 = 0xff;
+/// start value of irq vector
+pub const IRQ_VECTOR_START: u8 = 0x20;
+/// end value of irq vector
+pub const IRQ_VECTOR_END: u8 = 0xff;
 
 #[no_mangle]
 fn x86_trap_handler(tf: &mut TrapFrame) {

modules/axhal/src/lib.rs

@@ -77,3 +77,11 @@ pub use self::platform::platform_init;
 
 #[cfg(feature = "smp")]
 pub use self::platform::platform_init_secondary;
+
+/// PCI related operations
+pub mod pci {
+    #[cfg(all(target_arch = "x86_64", feature = "axalloc"))]
+    pub use super::platform::acpi::get_ecam_address;
+    #[cfg(all(target_arch = "x86_64", feature = "irq", feature = "axalloc"))]
+    pub use super::platform::acpi::get_pci_irq_vector;
+}

modules/axhal/src/platform/dummy/mod.rs

@@ -91,3 +91,16 @@ pub fn platform_init() {}
 /// Initializes the platform devices for secondary CPUs.
 #[cfg(feature = "smp")]
 pub fn platform_init_secondary() {}
+
+pub mod acpi {
+    #[cfg(feature = "irq")]
+    pub fn get_pci_irq_vector(bus: u8, device: u8, function: u8) -> Option<usize> {
+        None
+    }
+
+    use crate::mem::PhysAddr;
+    /// Get PCIe ECAM space physical address.
+    pub fn get_ecam_address() -> Option<PhysAddr> {
+        None
+    }
+}