riscv64: Add Zvbb (Vector Basic Bit-manipulation) extension support#13738
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rajeshgangam wants to merge 1 commit into
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riscv64: Add Zvbb (Vector Basic Bit-manipulation) extension support#13738rajeshgangam wants to merge 1 commit into
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Add support for the RISC-V Zvbb extension in the Cranelift backend. This adds the `has_zvbb` feature flag and implements instruction selection for the following Zvbb instructions: Two-operand (VecAluOpRRR): - vandn.vv / vandn.vx — vector AND-NOT - vrol.vv / vrol.vx — vector rotate left - vror.vv / vror.vx — vector rotate right Immediate (VecAluOpRRImm5): - vror.vi — vector rotate right by immediate Single-operand (VecAluOpRR, VXUNARY0 encoding): - vbrev.v — bit reverse - vbrev8.v — bit reverse within bytes - vrev8.v — byte reverse - vclz.v — count leading zeros - vctz.v — count trailing zeros - vcpop.v — population count Lowering rules (gated by has_zvbb): - band(x, bnot(y)) → vandn.vv / vandn.vx - popcnt → vcpop.v - rotl → vrol.vx - rotr → vror.vx Resolves bytecodealliance#7187
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Summary
Add support for the RISC-V Zvbb extension in the Cranelift backend, implementing instruction selection and encoding for 13 vector bit-manipulation instructions.
has_zvbbfeature flag for the riscv64 ISAvandn,vrol,vror(two-operand),vror.vi(immediate), andvbrev,vbrev8,vrev8,vclz,vctz,vcpop(single-operand VXUNARY0)has_zvbb:band(x, bnot(y))→vandn,popcnt→vcpop,rotl→vrol.vx,rotr→vror.vxInstructions implemented
vandn.vv/.vxband(x, bnot(y))vrol.vv/.vxrotl(vec, scalar)vror.vv/.vx/.virotr(vec, scalar)vbrev.vvbrev8.vvrev8.vvclz.vvctz.vvcpop.vpopcnt(vec)Note:
vclz,vctz,vbrev,vbrev8,vrev8have ISLE helpers and correct encoding but no lowering rules yet becauseclz,ctz,bitrev,bswapare scalar-only in Cranelift IR. They are ready for use when vector-typed versions of these ops are added.vwsll(widening shift left) is deferred to a follow-up PR due to the large number of widening combination rules needed.Resolves #7187
Test plan
test compile precise-outputtests verify correct instruction selection and encoding across i8x16, i32x4, i64x2 element types (zvbb.clif)test runruntime tests verify correctness under QEMU riscv64 withzvbb=true(zvbb-run.clif)has_zvbbis not set