Skip to content
@chipsalliance

CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

CHIPS Alliance Logo

🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.2k 623

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.4k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.5k 233

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.1k 337

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 867 228

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 740 180

Repositories

Showing 10 of 111 repositories
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 13 Apache-2.0 2 15 1 Updated Apr 17, 2025
  • rocket-chip Public

    Rocket Chip Generator

    chipsalliance/rocket-chip’s past year of commit activity
    Scala 3,412 1,161 241 65 Updated Apr 17, 2025
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge’s past year of commit activity
    SystemVerilog 21 Apache-2.0 5 19 5 Updated Apr 17, 2025
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 264 Apache-2.0 34 19 39 Updated Apr 17, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 14 Apache-2.0 10 53 13 Updated Apr 17, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 110 Apache-2.0 53 132 58 Updated Apr 17, 2025
  • rvdecoderdb Public

    The Scala parser to parse riscv/riscv-opcodes generate

    chipsalliance/rvdecoderdb’s past year of commit activity
    Nix 18 7 1 2 Updated Apr 17, 2025
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 273 Apache-2.0 82 19 1 Updated Apr 17, 2025
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 23 Apache-2.0 5 4 1 Updated Apr 17, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    C++ 38 LGPL-3.0 661 0 0 Updated Apr 17, 2025
View all repositories