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Add Surelog AST->UHDM SystemVerilog Constraints support #315

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alaindargelas opened this issue Apr 22, 2020 · 2 comments

Collaborator

alaindargelas commented Apr 22, 2020

Populate UHDM with all the SystemVerilog constraints objects from the Surelog AST and internal (new) datastructures.
Related to issue: https://github.com/alainmarcel/UHDM/issues/185

Collaborator Author

alaindargelas commented Apr 22, 2020

See:

https://github.com/alainmarcel/Surelog/blob/master/src/DesignCompile/CompileStmt.cpp
As an example for supporting SystemVerilog constructs,

https://github.com/alainmarcel/Surelog/blob/master/src/DesignCompile/CompileModule.cpp
For examples on how to process the AST (Derived verbatim from the grammar/SV3_1aParser.g4)
Use -d ast to get a debug dump of the AST

https://github.com/alainmarcel/Surelog/blob/master/src/DesignCompile/UhdmWriter.cpp
To add the new UHDM data model dumps.
Use -d uhdm to get a dump of the UHDM database.

Collaborator Author

alaindargelas commented Oct 2, 2020

@LoJeff are you ready to take a task like this one (with help)?

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