GitHub - cstratton/fpgaverilog: test project for handmade xc3s100/xc3s250e proof-of-concept board

Name	Name	Last commit message	Last commit date
Latest commit Chris Stratton Capture data to memory, play back with crude sorta-spi Aug 25, 2013 a073f42 · Aug 25, 2013 History 4 Commits
Makefile	Makefile	Makefile: don't ignore .ucf constraint (pinout) file!	Aug 24, 2013
README	README	initial commit of half working code	Aug 24, 2013
fpgatest.xise	fpgatest.xise	initial commit of half working code	Aug 24, 2013
top.lso	top.lso	initial commit of half working code	Aug 24, 2013
top.prj	top.prj	initial commit of half working code	Aug 24, 2013
top.ucf	top.ucf	Capture data to memory, play back with crude sorta-spi	Aug 25, 2013
top.ut	top.ut	initial commit of half working code	Aug 24, 2013
top.v	top.v	Capture data to memory, play back with crude sorta-spi	Aug 25, 2013
top.xst	top.xst	initial commit of half working code	Aug 24, 2013

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Experimental verilog code for custom hand made xc3s100e/xc3s250e FPGA board

Uses a Makefile to build with ISE 11.1 outside of the IDE

test project for handmade xc3s100/xc3s250e proof-of-concept board

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