Merge pull request #622 from diffblue/error_first_line1

Verilog: KNOWNBUG test for input file without newline

Author: tautschnig

regression/verilog/modules/error_first_line1.desc

@@ -0,0 +1,10 @@
+KNOWNBUG
+error_first_line1.v
+
+
+^file error_first_line1.v: syntax error
+^EXIT=1$
+^SIGNAL=0$
+--
+--
+The line number is missing in the error message.

regression/verilog/modules/error_first_line1.v

@@ -0,0 +1 @@
+module test(some syntax error); // no newline