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Pull requests: diffblue/hw-cbmc

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Pull requests list

Verilog: strengthen typing in verilog_synthesist::instantiate_ports cleanup Verilog
#1259 opened Sep 5, 2025 by kroening Loading…
Verilog: module port declarations with default value Verilog
#1258 opened Sep 4, 2025 by kroening Loading…
Verilog: add Verilog type to lowered array type Verilog
#1257 opened Sep 3, 2025 by kroening Loading…
Verilog: fix for bit select on boolean argument Verilog
#1256 opened Sep 2, 2025 by kroening Loading…
KNOWNBUG test for function in compilation unit scope Tests Verilog
#1255 opened Sep 2, 2025 by kroening Loading…
Verilog: KNOWNBUG test for module port with value Tests Verilog
#1254 opened Sep 1, 2025 by kroening Loading…
Verilog: KNOWNBUG test for conversion of packed array Tests Verilog
#1253 opened Sep 1, 2025 by kroening Loading…
Verilog: Tests for constant folding of index expressions Tests Verilog
#1252 opened Sep 1, 2025 by kroening Loading…
Verilog: reject use of SVA sequences and properties as Boolean expression Verilog
#1248 opened Aug 28, 2025 by kroening Loading…
2
SystemVerilog .* Verilog
#1240 opened Aug 26, 2025 by kroening • Draft
SMV: union operator SMV
#1186 opened Jul 7, 2025 by kroening • Draft
split up ltl_sva_to_stringt::rec cleanup engines
#1171 opened Jun 27, 2025 by kroening • Draft
SVA: strengthen typing of sva_sequence_concatenation_exprt cleanup
#1161 opened Jun 17, 2025 by kroening • Draft
1
Verilog: $isunknown Verilog
#1149 opened Jun 9, 2025 by kroening Loading…
1
NeurIPS 2025 SystemVerilog benchmarks
#1147 opened Jun 6, 2025 by kroening Loading…
SMV: bit selection operator SMV
#1113 opened May 18, 2025 by kroening • Draft
SMV: expression typechecker now post-traversal SMV
#1040 opened Mar 28, 2025 by kroening Loading…
2
SVA monitor engines Verilog
#1011 opened Feb 25, 2025 by kroening • Draft
SystemVerilog: interface instantiation Verilog
#972 opened Feb 6, 2025 by kroening • Draft
SystemVerilog: declarations in named blocks in tasks/functions Verilog
#970 opened Feb 6, 2025 by kroening • Draft
1
SystemVerilog: preserve scopes between compilation units Verilog
#963 opened Feb 4, 2025 by kroening • Draft
SystemVerilog: create identifier expressions in scanner Verilog
#953 opened Jan 29, 2025 by kroening • Draft
Add chipsalliance/sv-tests to CI
#939 opened Jan 17, 2025 by kroening • Draft
aval/bval lowering for reduction operators Verilog
#930 opened Jan 16, 2025 by kroening • Draft
vlindex: fix parsing for constraint_block
#924 opened Jan 6, 2025 by kroening • Draft
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