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lines changed Original file line number Diff line number Diff line change 6
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* Verilog: allow indexed part select
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* word-level BMC: fix for F/s_eventually and U/s_until
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* IC3: liveness to safety translation
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+ * Assumptions are not disabled when using --property
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# EBMC 5.2
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CORE
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- main .v
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+ assume1 .v
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--module main --bound 3 --aig --vl2smv-extensions
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^\[main\.property\.a1\] assume always 10 <= main\.a && main\.a <= 100: ASSUMED$
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^\[main\.property\.p1\] always main\.a != 200: PROVED up to bound 3$
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+ CORE
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+ assume2.sv
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+ --bound 0 --property main.p1
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+ ^\[main\.a1\] assume always 10 <= main\.a && main\.a <= 100: ASSUMED$
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+ ^\[main\.p1\] always main\.a != 200: PROVED up to bound 0$
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+ ^EXIT=0$
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+ ^SIGNAL=0$
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+ module main (input [31 : 0 ] a);
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+
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+ a1: assume final (10 <= a && a<= 100 );
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+
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+ p1 : assert final (a!= 200 );
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+
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+ // would fail
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+ p2 : assert final (a!= 20 );
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+
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+ endmodule
Original file line number Diff line number Diff line change @@ -110,8 +110,10 @@ bool ebmc_propertiest::select_property(
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{
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std::string property = cmdline.get_value (" property" );
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+ // disable all assertions (not: assumptions)
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for (auto &p : properties)
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- p.status = propertyt::statust::DISABLED;
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+ if (!p.is_assumed ())
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+ p.status = propertyt::statust::DISABLED;
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bool found = false ;
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