Skip to content

Commit 75cb2d0

Browse files
authored
Merge pull request #665 from diffblue/indexed_nexttime
SVA: implement indexed nexttime
2 parents 1968fe8 + e7f11dd commit 75cb2d0

File tree

4 files changed

+19
-9
lines changed

4 files changed

+19
-9
lines changed

regression/verilog/SVA/nexttime1.desc

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
1-
KNOWNBUG
1+
CORE
22
nexttime1.sv
33
--module main --bound 10
4-
^\[main\.assert\.1\] s_nexttime\[0\] main\.counter == 0: PROVED up to bound 10$
5-
^\[main\.assert\.2\] s_nexttime\[1\] main\.counter == 1: PROVED up to bound 10$
6-
^\[main\.assert\.3\] nexttime\[8\] main\.counter == 8: PROVED up to bound 10$
7-
^EXIT=10$
4+
^\[main\.p1\] s_nexttime\[0\] main\.counter == 0: PROVED up to bound 10$
5+
^\[main\.p2\] s_nexttime\[1\] main\.counter == 1: PROVED up to bound 10$
6+
^\[main\.p3\] nexttime\[8\] main\.counter == 8: PROVED up to bound 10$
7+
^EXIT=0$
88
^SIGNAL=0$
99
--
1010
^warning: ignoring

src/temporal-logic/normalize_property.cpp

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -151,12 +151,20 @@ exprt normalize_property(exprt expr)
151151
expr = normalize_pre_sva_or(to_sva_or_expr(expr));
152152
else if(expr.id() == ID_sva_nexttime)
153153
{
154-
if(!to_sva_nexttime_expr(expr).is_indexed())
155-
expr = X_exprt{to_sva_nexttime_expr(expr).op()};
154+
auto &nexttime_expr = to_sva_nexttime_expr(expr);
155+
if(nexttime_expr.is_indexed())
156+
expr = sva_ranged_always_exprt{
157+
nexttime_expr.index(), nexttime_expr.index(), nexttime_expr.op()};
158+
else
159+
expr = X_exprt{nexttime_expr.op()};
156160
}
157161
else if(expr.id() == ID_sva_s_nexttime)
158162
{
159-
if(!to_sva_s_nexttime_expr(expr).is_indexed())
163+
auto &nexttime_expr = to_sva_s_nexttime_expr(expr);
164+
if(nexttime_expr.is_indexed())
165+
expr = sva_s_always_exprt{
166+
nexttime_expr.index(), nexttime_expr.index(), nexttime_expr.op()};
167+
else
160168
expr = X_exprt{to_sva_s_nexttime_expr(expr).op()};
161169
}
162170
else if(expr.id() == ID_sva_cycle_delay)

src/temporal-logic/normalize_property.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,9 @@ Author: Daniel Kroening, [email protected]
2222
/// sva_overlapped_implication --> ¬a ∨ b if a and b are not SVA sequences
2323
/// sva_non_overlapped_implication --> ¬a ∨ Xb if a and b are not SVA sequences
2424
/// sva_nexttime φ --> Xφ
25+
/// sva_nexttime[i] φ --> sva_always[i:i] φ
2526
/// sva_s_nexttime φ --> Xφ
27+
/// sva_s_nexttime[i] φ --> sva_s_always[i:i] φ
2628
/// sva_if --> ? :
2729
/// a sva_disable_iff b --> a ∨ b
2830
/// a sva_accept_on b --> a ∨ b

src/verilog/sva_expr.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -324,7 +324,7 @@ class sva_ranged_always_exprt : public sva_ranged_predicate_exprt
324324
public:
325325
sva_ranged_always_exprt(exprt lower, exprt upper, exprt op)
326326
: sva_ranged_predicate_exprt(
327-
ID_sva_always,
327+
ID_sva_ranged_always,
328328
std::move(lower),
329329
std::move(upper),
330330
std::move(op))

0 commit comments

Comments
 (0)