Verilog: KNOWNBUG test for power operator

Author: kroening

regression/verilog/expressions/power1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+power1.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+Lowering for power on three-valued logic is missing.

regression/verilog/expressions/power1.sv

@@ -0,0 +1,12 @@
+module main;
+
+  property01: assert final (2**0==1);
+  property02: assert final (2**1==2);
+  property03: assert final ((-2)**1==-2);
+  property04: assert final (2**2==4);
+  property05: assert final (2**-1==0);
+  property06: assert final ($bits(3'd2**2)==3);
+  property07: assert final (2**'bx===32'bx);
+  property08: assert final ('bx**2===32'bx);
+
+endmodule