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regression/verilog/property Expand file tree Collapse file tree 5 files changed +44
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lines changed Original file line number Diff line number Diff line change 1
- KNOWNBUG
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+ CORE
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named_property5.sv
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+ ^file .* line 8: cannot use SVA property as an expression$
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^EXIT=2$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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- This should be rejected.
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- KNOWNBUG
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+ CORE
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named_property6.sv
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^EXIT=2$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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- This should be rejected.
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+ CORE
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+ named_property7.sv
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+
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+ ^EXIT=2$
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+ ^SIGNAL=0$
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+ --
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+ ^warning: ignoring
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+ --
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+ module main ;
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+
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+ property P ;
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+ 1
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+ endproperty
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+
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+ // This should be rejected
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+ wire x = P + P ;
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+
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+ endmodule
Original file line number Diff line number Diff line change @@ -121,6 +121,17 @@ void verilog_typecheck_exprt::propagate_type(
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if (expr.type ()==type)
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return ;
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+ if (expr.type ().id () == ID_verilog_sva_sequence)
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+ {
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+ throw errort{}.with_location (expr.source_location ())
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+ << " cannot use SVA sequence as an expression" ;
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+ }
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+ else if (expr.type ().id () == ID_verilog_sva_property)
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+ {
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+ throw errort{}.with_location (expr.source_location ())
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+ << " cannot use SVA property as an expression" ;
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+ }
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+
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vtypet vt_from=vtypet (expr.type ());
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vtypet vt_to =vtypet (type);
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@@ -2174,8 +2185,19 @@ Function: verilog_typecheck_exprt::make_boolean
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void verilog_typecheck_exprt::make_boolean (exprt &expr)
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{
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- if (expr.type ().id ()!=ID_bool)
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+ if (expr.type ().id () == ID_verilog_sva_sequence)
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+ {
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+ throw errort{}.with_location (expr.source_location ())
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+ << " cannot use SVA sequence as an expression" ;
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+ }
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+ else if (expr.type ().id () == ID_verilog_sva_property)
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+ {
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+ throw errort{}.with_location (expr.source_location ())
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+ << " cannot use SVA property as an expression" ;
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+ }
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+ else if (expr.type ().id () != ID_bool)
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{
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+ // everything else can be converted to Boolean
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mp_integer value;
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if (!to_integer_non_constant (expr, value))
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expr = make_boolean_expr (value != 0 );
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