File tree Expand file tree Collapse file tree 2 files changed +19
-0
lines changed
regression/verilog/expressions Expand file tree Collapse file tree 2 files changed +19
-0
lines changed Original file line number Diff line number Diff line change @@ -21,4 +21,12 @@ module main(in);
21
21
always assert property4:
22
22
{{ 1 { 1'b0 }}, in } == in;
23
23
24
+ // constant folding
25
+ parameter P = { 2 { 2'b01 } };
26
+
27
+ wire [P:0 ] some_wire;
28
+
29
+ always assert property5:
30
+ P == 'b0101;
31
+
24
32
endmodule
Original file line number Diff line number Diff line change @@ -1552,6 +1552,17 @@ exprt verilog_typecheck_exprt::elaborate_constant_expression(exprt expr)
1552
1552
expr = notequal_exprt (
1553
1553
reduction_or.op (), from_integer (0 , reduction_or.op ().type ()));
1554
1554
}
1555
+ else if (expr.id () == ID_replication)
1556
+ {
1557
+ auto &replication = to_replication_expr (expr);
1558
+ auto times = numeric_cast_v<std::size_t >(replication.times ());
1559
+ // lower to a concatenation
1560
+ exprt::operandst ops;
1561
+ ops.reserve (times);
1562
+ for (std::size_t i = 0 ; i < times; i++)
1563
+ ops.push_back (replication.op ());
1564
+ expr = concatenation_exprt{ops, expr.type ()};
1565
+ }
1555
1566
1556
1567
// We fall back to the simplifier to approximate
1557
1568
// the standard's definition of 'constant expression'.
You can’t perform that action at this time.
0 commit comments