Merge pull request #624 from diffblue/enum1-aig

Netlist conversion: do not convert types

Author: tautschnig

regression/verilog/enums/enum1.aig.desc

@@ -0,0 +1,11 @@
+CORE
+enum1.sv
+--bound 3 --numbered-trace --aig
+^EXIT=10$
+^SIGNAL=0$
+^\[main\.p1\] always main\.my_light != main.YELLOW2: REFUTED$
+^main\.my_light@0 = main\.RED$
+^main\.my_light@1 = main\.YELLOW1$
+^main\.my_light@2 = main\.GREEN$
+^main\.my_light@3 = main\.YELLOW2$
+--

src/trans-netlist/trans_to_netlist.cpp

@@ -207,6 +207,8 @@ void convert_trans_to_netlistt::map_vars(
     else if (symbol.type.id() == ID_module ||
              symbol.type.id() == ID_module_instance)
       return; // ignore modules
+    else if(symbol.is_type)
+      return; // ignore types
     else if (symbol.is_input)
       vartype = var_mapt::vart::vartypet::INPUT;
     else if (symbol.is_state_var)