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Few updates to WB VIP #1

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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
//////////////////////////////////////////////////////////////////////////////
// Modifications:
// 2017-03-31: by Jan Pospisil ([email protected])
// * added transaction timeout
//////////////////////////////////////////////////////////////////////////////

`ifndef WISHBONE_B3_COMMON_METHODS__SV
`define WISHBONE_B3_COMMON_METHODS__SV
Expand All @@ -21,6 +25,7 @@ class wishbone_b3_common_methods #(ADR_W = 32, DAT_W = 64, TAG_W = 1) extends uv
`uvm_object_param_utils( wishbone_b3_common_methods #(.ADR_W(ADR_W), .DAT_W(DAT_W), .TAG_W(TAG_W)) )

virtual wishbone_b3_if #(.DAT_W(DAT_W), .ADR_W(ADR_W), .TAG_W(TAG_W)) sigs;
wishbone_b3_master_cfg cfg;

extern function new(string name = "wishbone_b3_common_methods");
extern virtual task wait_for_response(output e_wishbone_b3_response response);
Expand All @@ -35,13 +40,22 @@ endfunction: new

//------------------------------------------------------------------------//
task wishbone_b3_common_methods::wait_for_response(output e_wishbone_b3_response response);
wait( (sigs.m_drv_cb.ack === 1'b1) || (sigs.m_drv_cb.err === 1'b1) || (sigs.m_drv_cb.rty === 1'b1) );

// specifically not if-else so the value will overwrite if there is an erroneous multiple
// response.
if (sigs.m_drv_cb.ack === 1'b1) response = WB_B3_RESPONSE_ACK_OK;
if (sigs.m_drv_cb.rty === 1'b1) response = WB_B3_RESPONSE_ACK_RTY;
if (sigs.m_drv_cb.err === 1'b1) response = WB_B3_RESPONSE_ACK_ERR;
fork
begin
wait( (sigs.m_drv_cb.ack === 1'b1) || (sigs.m_drv_cb.err === 1'b1) || (sigs.m_drv_cb.rty === 1'b1) );
// specifically not if-else so the value will overwrite if there is an erroneous multiple
// response.
if (sigs.m_drv_cb.ack === 1'b1) response = WB_B3_RESPONSE_ACK_OK;
if (sigs.m_drv_cb.rty === 1'b1) response = WB_B3_RESPONSE_ACK_RTY;
if (sigs.m_drv_cb.err === 1'b1) response = WB_B3_RESPONSE_ACK_ERR;
end
begin
#cfg.timeout `uvm_error("WB_MON", "Transaction time-out!")
response = WB_B3_RESPONSE_ACK_ERR;
@(sigs.m_drv_cb); // synchronize driver operations to the current clock
end
join_any
disable fork;

endtask: wait_for_response

Expand Down
7 changes: 7 additions & 0 deletions src/wishbone_b3/wishbone_b3_if.sv
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
//////////////////////////////////////////////////////////////////////////////
// Modifications:
// 2016-08-11: by Jan Pospisil ([email protected])
// * added timeunit/timeprecision to WB interface
//////////////////////////////////////////////////////////////////////////////

`ifndef WISHBONE_B3_IF__SV
`define WISHBONE_B3_IF__SV
Expand Down Expand Up @@ -65,6 +69,9 @@ interface wishbone_b3_if #(DAT_W = 64, ADR_W = 32, TAG_W = 1) (input bit clk)
//parameter ADR_W = 32; // address port width
//parameter TAG_W = 1; // default tag widths are 1 bit

timeunit 1ns;
timeprecision 1ps;

localparam SEL_W = (DAT_W/8); // 1 select bit per data byte, divide by 8

/// common signals ///
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
//////////////////////////////////////////////////////////////////////////////
// Modifications:
// 2017-03-31: by Jan Pospisil ([email protected])
// * added transaction timeout
//////////////////////////////////////////////////////////////////////////////

`ifndef WISHBONE_B3_MASTER_AGENT__SV
`define WISHBONE_B3_MASTER_AGENT__SV
Expand Down Expand Up @@ -74,8 +78,8 @@ function void wishbone_b3_master_agent::build_phase(uvm_phase phase);

if ( sigs == null ) `uvm_fatal(get_type_name(), $sformatf("%s interface not set!", this.get_full_name() ) )

// put cfg object in config_db so sequences can use it
uvm_config_db #(wishbone_b3_master_cfg)::set(null, {get_full_name(), ".seqr"}, "cfg", cfg);
// put cfg object in config_db
uvm_config_db #(wishbone_b3_master_cfg)::set(null, "*", "cfg", cfg);


mon = td_wishbone_b3_monitor::type_id::create("mon", this);
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
//////////////////////////////////////////////////////////////////////////////
// Modifications:
// 2017-03-31: by Jan Pospisil ([email protected])
// * added transaction timeout
//////////////////////////////////////////////////////////////////////////////

`ifndef WISHBONE_B3_MASTER_CFG__SV
`define WISHBONE_B3_MASTER_CFG__SV
Expand All @@ -24,9 +28,14 @@ class wishbone_b3_master_cfg extends uvm_object;
// Variables: is_active
// Agent can be defined passive or active.
rand uvm_active_passive_enum is_active;

// Variable: timeout
// Time-out for bus accesses.
int timeout = 0;

`uvm_object_utils_begin(wishbone_b3_master_cfg)
`uvm_field_enum(uvm_active_passive_enum, is_active, UVM_ALL_ON)
`uvm_field_int(timeout, UVM_ALL_ON)
`uvm_object_utils_end

extern function new(string name = "wishbone_b3_master_cfg");
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,16 @@
// See the License for the specific language governing permissions and
// limitations under the License.
//////////////////////////////////////////////////////////////////////////////
// Modifications:
// 2016-06-08: by Jan Pospisil ([email protected])
// * removed constructs which seems not to be supported in UVM 1.2
// * fixed reset logic (WB_B3 Rule 2.30)
// * do not issue a transaction when reset is active
// 2016-06-13: by Jan Pospisil ([email protected])
// * fixed beginning of transaction for closely successive operations
// 2017-03-31: by Jan Pospisil ([email protected])
// * added transaction timeout
//////////////////////////////////////////////////////////////////////////////

`ifndef WISHBONE_B3_DRIVER__SV
`define WISHBONE_B3_DRIVER__SV
Expand All @@ -25,6 +35,7 @@ class wishbone_b3_master_driver #(ADR_W = 32, DAT_W = 64, TAG_W = 1) extends uv

typedef wishbone_b3_sequence_item #(.ADR_W(ADR_W), .DAT_W(DAT_W), .TAG_W(TAG_W)) td_wishbone_b3_sequence_item;
virtual wishbone_b3_if #(.DAT_W(DAT_W), .ADR_W(ADR_W), .TAG_W(TAG_W)) sigs;
wishbone_b3_master_cfg cfg;
wishbone_b3_common_methods #(.DAT_W(DAT_W), .ADR_W(ADR_W), .TAG_W(TAG_W)) common_mthds;

extern function new(string name, uvm_component parent);
Expand All @@ -46,12 +57,12 @@ endfunction: new
function void wishbone_b3_master_driver::build_phase(uvm_phase phase);
super.build_phase(phase);

phase.raise_objection(this);
// get the configuration object
if(!uvm_config_db #(wishbone_b3_master_cfg)::get(this, "", "cfg", cfg)) `uvm_fatal(get_type_name(), "wishbone_b3_master_cfg config_db lookup failed")

common_mthds = wishbone_b3_common_methods #(.DAT_W(DAT_W), .ADR_W(ADR_W), .TAG_W(TAG_W))::type_id::create("common_mthds", this);
common_mthds.sigs = sigs;

phase.drop_objection(this);
common_mthds.cfg = cfg;

endfunction: build_phase

Expand Down Expand Up @@ -87,8 +98,13 @@ endtask: run_phase

//------------------------------------------------------------------------//
task wishbone_b3_master_driver::write_transaction(td_wishbone_b3_sequence_item s_item);
// wait for inactive reset
wait(sigs.rst_i === 1'b0);

//stating a cycle
// wait for free bus
wait(~sigs.m_drv_cb.ack & ~sigs.m_drv_cb.err & ~sigs.m_drv_cb.rty);

// stating a cycle
sigs.m_drv_cb.cyc <= 1'b1;
sigs.m_drv_cb.tgc <= '0; // cycle tag currently not supported

Expand All @@ -113,6 +129,12 @@ endtask: write_transaction

//------------------------------------------------------------------------//
task wishbone_b3_master_driver::read_transaction(td_wishbone_b3_sequence_item s_item);
// wait for inactive reset
wait(sigs.rst_i === 1'b0);

// wait for free bus
wait(~sigs.m_drv_cb.ack & ~sigs.m_drv_cb.err & ~sigs.m_drv_cb.rty);

//stating a cycle
sigs.m_drv_cb.cyc <= 1'b1;
sigs.m_drv_cb.tgc <= '0; // cycle tag currently not supported
Expand Down Expand Up @@ -142,7 +164,7 @@ endtask: read_transaction
// This isn't being sent through a clocking block since the
// reset is asynchronous and there is no guarantee the clock is toggling
task wishbone_b3_master_driver::drive_x_to_outputs_during_reset();
wait(sigs.rst_i === 1'b0);
wait(sigs.rst_i === 1'b1);
sigs.dat_o = 'x;
sigs.tgd_o = 'x;
sigs.adr = 'x;
Expand All @@ -154,7 +176,7 @@ task wishbone_b3_master_driver::drive_x_to_outputs_during_reset();
sigs.tgc = 'x;
sigs.we = 'x;

wait(sigs.rst_i === 1'b1);
wait(sigs.rst_i === 1'b0);
sigs.dat_o = '0;
sigs.tgd_o = '0;
sigs.adr = '0;
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,12 @@
// See the License for the specific language governing permissions and
// limitations under the License.
//////////////////////////////////////////////////////////////////////////////
// Modifications:
// 2016-06-08: by Jan Pospisil ([email protected])
// * removed constructs which seems not to be supported in UVM 1.2
// 2017-03-31: by Jan Pospisil ([email protected])
// * added transaction timeout
//////////////////////////////////////////////////////////////////////////////

`ifndef WISHBONE_B3_MONITOR__SV
`define WISHBONE_B3_MONITOR__SV
Expand All @@ -26,6 +32,7 @@ class wishbone_b3_monitor #(ADR_W = 32, DAT_W = 64, TAG_W = 1) extends uvm_monit
typedef wishbone_b3_sequence_item #(.ADR_W(ADR_W), .DAT_W(DAT_W), .TAG_W(TAG_W)) td_wishbone_b3_sequence_item;

virtual wishbone_b3_if #(.DAT_W(DAT_W), .ADR_W(ADR_W), .TAG_W(TAG_W)) sigs;
wishbone_b3_master_cfg cfg;
uvm_analysis_port #(td_wishbone_b3_sequence_item) analysis_port;
wishbone_b3_common_methods #(.DAT_W(DAT_W), .ADR_W(ADR_W), .TAG_W(TAG_W)) common_mthds;

Expand All @@ -49,13 +56,14 @@ endfunction: new
function void wishbone_b3_monitor::build_phase(uvm_phase phase);
super.build_phase(phase);

phase.raise_objection(this);

this.analysis_port = new("analysis_port", this);

// get the configuration object
if(!uvm_config_db #(wishbone_b3_master_cfg)::get(this, "", "cfg", cfg)) `uvm_fatal(get_type_name(), "wishbone_b3_master_cfg config_db lookup failed")

common_mthds = wishbone_b3_common_methods #(.DAT_W(DAT_W), .ADR_W(ADR_W), .TAG_W(TAG_W))::type_id::create("common_mthds", this);
common_mthds.sigs = sigs;

phase.drop_objection(this);
common_mthds.cfg = cfg;

endfunction: build_phase

Expand Down
21 changes: 14 additions & 7 deletions src/wishbone_b3/wishbone_b3_package.sv
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,13 @@
// See the License for the specific language governing permissions and
// limitations under the License.
//////////////////////////////////////////////////////////////////////////////
// Modifications:
// 2016-06-08: by Jan Pospisil ([email protected])
// * file extensions renamed (.sv for compilable units, .svh for
// include-able units)
// 2017-03-31: by Jan Pospisil ([email protected])
// * added transaction timeout
//////////////////////////////////////////////////////////////////////////////

`ifndef WISHBONE_B3_PACKAGE__SV
`define WISHBONE_B3_PACKAGE__SV
Expand Down Expand Up @@ -52,13 +59,13 @@ package wishbone_b3_package;
WB_B3_RESPONSE_ACK_RTY = 2
} e_wishbone_b3_response;

`include "wishbone_b3_common_methods.sv"
`include "wishbone_b3_master_cfg.sv"
`include "wishbone_b3_sequence_item.sv"
`include "wishbone_b3_master_driver.sv"
`include "wishbone_b3_monitor.sv"
`include "wishbone_b3_reg_adapter.sv"
`include "wishbone_b3_master_agent.sv"
`include "wishbone_b3_master_cfg.svh"
`include "wishbone_b3_common_methods.svh"
`include "wishbone_b3_sequence_item.svh"
`include "wishbone_b3_master_driver.svh"
`include "wishbone_b3_monitor.svh"
`include "wishbone_b3_reg_adapter.svh"
`include "wishbone_b3_master_agent.svh"

endpackage: wishbone_b3_package

Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,14 @@
// See the License for the specific language governing permissions and
// limitations under the License.
//////////////////////////////////////////////////////////////////////////////
// Modifications:
// 2016-06-14: by Jan Pospisil ([email protected])
// * added get_type_name() and convert2string() methods; now this
// call is possible:
// $sformatf(
// "Transaction \"%s\" received: %s",
// t.get_type_name(), t.convert2string())
//////////////////////////////////////////////////////////////////////////////

`ifndef WISHBONE_B3_SEQUENCE_ITEM__SV
`define WISHBONE_B3_SEQUENCE_ITEM__SV
Expand Down Expand Up @@ -53,7 +61,9 @@ class wishbone_b3_sequence_item #(ADR_W = 32, DAT_W = 64, TAG_W = 1) extends uvm
`uvm_field_enum( e_wishbone_b3_response, response_e, UVM_ALL_ON)
`uvm_object_utils_end

extern function new(string name = "wishbone_b3_sequence_item");
extern function new(string name = "wishbone_b3_sequence_item");
extern function string get_type_name();
extern function string convert2string();

extern constraint response_c;
extern constraint select_c;
Expand All @@ -68,6 +78,25 @@ function wishbone_b3_sequence_item::new(string name = "wishbone_b3_sequence_item

endfunction: new

//------------------------------------------------------------------------//
// function: get_type_name
// override of super's method for parametrized class
function string wishbone_b3_sequence_item::get_type_name();
return "wishbone_b3_sequence_item";

endfunction

//------------------------------------------------------------------------//
// function: convert2string
// for custom displaying class content
function string wishbone_b3_sequence_item::convert2string();
// convert2string = "TBD";
convert2string = $sformatf(
"direction_e = %s, address = 0x%H, data = 0x%H, select = 0b%B, response_e = %s",
direction_e.name(), address, data, select, response_e.name());

endfunction

//------------------------------------------------------------------------//
// constraint: response_c
// constraints variable <response_e>. Default value = WB_B3_RESPONSE_ACK_ERR.
Expand Down