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pre-commit: PR165877 #3008
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Diff moderunner: ariselab-64c-docker 1304 files changed, 1286865 insertions(+), 1285622 deletions(-) +18 libquic/string_number_conversions.ll |
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The provided patch contains numerous changes across multiple LLVM IR files, primarily focused on improving type safety, reducing unnecessary truncations, and optimizing control flow. Here are the major changes:
These changes collectively improve performance by reducing instruction count, enhancing type precision, and simplifying control flow, which can lead to better optimization opportunities in later compilation stages. model: qwen-plus-latest |
| %91 = add nuw nsw i16 %90, %87 | ||
| %92 = lshr exact i16 %86, 1 | ||
| %93 = add nuw nsw i16 %91, %92 | ||
| %94 = add nsw i16 %93, -132 |
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Regression.
| %mul = mul nsw i64 %spec.select.i, 3600 | ||
| %add25 = add nsw i64 %minuteOffset.0, %mul | ||
| %sext = shl i64 %add25, 32 | ||
| %conv27 = ashr exact i64 %sext, 32 |
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Regression
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Although I also don't get why this might be beneficial, but this is actually a goal of this transformation to remove extra sext and calculate in a wider range. My patch just applies it in more cases. If this is a regression, we should remove that transformation altogether.
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I mean the sext_inreg pattern is not eliminated after evaluating the expression in a wider type.
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I believe it's added because we can't prove that higher known bits of the %add25 are 0s. It's still part of a normal workings of this transformation.
Do you mind expanding a bit what would be the expectation about the PR and dealing with marked regressions like this one. Thanks!
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I believe it's added because we can't prove that higher known bits of the %add25 are 0s.
It doesn't require high 32 0s. We can eliminate the sext_inreg if %add25 has at least 33 sign bits (See ComputeNumSignBits). Obviously the condition holds because we can compute the expression in i32 without signed overflow. It is the last chance that we can remove the shl+ashr pair since we will lose the sign bit information after the transformation (binop nsw i32 -> binop nsw i64).
I don't mean to block this pr as the net effect is positive. It's just a missed optimization exposed by this patch :)
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Ah, makes perfect sense. Thanks for a clear explanation!
Link: llvm/llvm-project#165877
Requested by: @dtcxzyw