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N6 IC Selection Fix #5383

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Merged
xoviat merged 5 commits into from
Feb 4, 2026
+10 −6
Merged

N6 IC Selection Fix #5383

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40c8979
N6 PLL3 / 4 Support
jake-taf Feb 4, 2026
b152e85
Fix division
jake-taf Feb 4, 2026
02addf8
Fix IC Selection Names
jake-taf Feb 4, 2026
a71b7f0
Remove warning
jake-taf Feb 4, 2026
d9ae8f8
Use new stm32-data
jake-taf Feb 4, 2026
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4 changes: 2 additions & 2 deletions embassy-stm32/Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -203,11 +203,11 @@ aligned = "0.4.3"
heapless = "0.9.1"

# stm32-metapac = { version = "19" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2846f7ae645cef28b8b9728927e3482fcfd74f6e" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-31bad6b0b9f30858891173e422df356f21a70870" }

[build-dependencies]
# stm32-metapac = { version = "19", default-features = false, features = ["metadata"]}
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2846f7ae645cef28b8b9728927e3482fcfd74f6e", default-features = false, features = ["metadata"] }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-31bad6b0b9f30858891173e422df356f21a70870", default-features = false, features = ["metadata"] }

proc-macro2 = "1.0.36"
quote = "1.0.15"
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12 changes: 8 additions & 4 deletions embassy-stm32/src/rcc/n6.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -224,6 +224,8 @@ struct ClocksInput {
hse: Option<Hertz>,
pll1: Option<Hertz>,
pll2: Option<Hertz>,
pll3: Option<Hertz>,
pll4: Option<Hertz>,
}

fn init_clocks(config: Config, input: &ClocksInput) -> ClocksOutput {
Expand Down Expand Up @@ -388,8 +390,8 @@ fn init_clocks(config: Config, input: &ClocksInput) -> ClocksOutput {
let src_freq = match source {
Icsel::PLL1 => unwrap!(input.pll1),
Icsel::PLL2 => unwrap!(input.pll2),
Icsel::HSI_OSC_DIV4 => Hertz(unwrap!(input.hsi).0 / 4),
Icsel::HSI_OSC_DIV8 => Hertz(unwrap!(input.hsi).0 / 8),
Icsel::PLL3 => unwrap!(input.pll3),
Icsel::PLL4 => unwrap!(input.pll4),
};
let div = (divider.to_bits() as u32) + 1;
Hertz(src_freq.0 / div)
Expand All @@ -404,8 +406,8 @@ fn init_clocks(config: Config, input: &ClocksInput) -> ClocksOutput {
let src_freq = match ic2.source {
Icsel::PLL1 => unwrap!(input.pll1),
Icsel::PLL2 => unwrap!(input.pll2),
Icsel::HSI_OSC_DIV4 => Hertz(unwrap!(input.hsi).0 / 4),
Icsel::HSI_OSC_DIV8 => Hertz(unwrap!(input.hsi).0 / 8),
Icsel::PLL3 => unwrap!(input.pll3),
Icsel::PLL4 => unwrap!(input.pll4),
};
let div = (ic2.divider.to_bits() as u32) + 1;
Hertz(src_freq.0 / div)
Expand Down Expand Up @@ -1247,6 +1249,8 @@ pub(crate) unsafe fn init(config: Config) {
hse: osc.hse,
pll1: osc.pll1,
pll2: osc.pll2,
pll3: osc.pll3,
pll4: osc.pll4,
};
let clocks = init_clocks(config, &clock_inputs);

Expand Down