All pull requests

Pull requests

• liblitedram/sdram: CK phase leveling: per-bit read eye refinement under BIST traffic

  #2681·enjoy-digital opened Oct 18, 2026Owner·

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• Fix code block syntax highlighting in README.md to avoid copy/paste issues with "$"

  #2660·ohault opened Oct 6, 2026·

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• soc/video: Share GTP HDMI TX clock and add board diagnostics

  #2655·enjoy-digital opened Sep 29, 2026Owner·

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• litex_setup: add package uninstall with preview and confirmation

  #2654·enjoy-digital opened Sep 29, 2026Owner·

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• liblitesdcard: test main-RAM receive bounce buffer on coherent VexiiRiscv

  #2650·enjoy-digital opened Sep 29, 2026Owner·

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• liblitedram: add USNativeDDRPHY BIOS calibration

  #2618·AEW2015 opened Sep 17, 2026Contributor·

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  4

• interconnect/csr_bus: ensure CSRBank's CSRs fit in one CSR page

  #2588·AUTHENSOR opened Sep 11, 2026·

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  1

  1

• tools/litex_server: Use a unique port for JTAGUART instances

  #2562·storborg opened Sep 2, 2026Contributor·

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• builder/gen: add full hierarchical Verilog generation

  #2543·hansfbaier opened Jul 27, 2026Contributor·

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  2

• examples: add standalone cocotb+Verilator sim example (CPU-less)

  answered-waiting-feedbacknew-feature
  #2515·vs4848 opened Jul 9, 2026·

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  4

• soc/uart: add automatic TX/RX swap detection

  #2507·enjoy-digital opened Jul 8, 2026Owner·

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• soc/uart: add shared UARTBone mux

  #2506·enjoy-digital opened Jul 8, 2026Owner·

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• soc: Add explicit CSR region aliases

  #2490·enjoy-digital opened Jun 29, 2026Owner·

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• cpu/microwatt: boot Linux (RAM@0 / ROM@0xFFFE0000) + ppc64 DTS (litex#2306)

  #2485·enjoy-digital opened Jun 25, 2026Owner·

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• build/efinix: Add unified netlist flow support.

  #2480·enjoy-digital opened Jun 11, 2026Owner·

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  1

• PoC: model-based AXI-Lite tests + converter regression

  #2402·cklarhorst opened Jan 21, 2026Contributor·

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  1

• Add GenericTAP and enable JTAGBone access via jtagremote in litex_sim

  #2398·cklarhorst opened Jan 13, 2026Contributor·

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  1

• integration/builder: Add bios selftest option

  #2393·cklarhorst opened Jan 9, 2026Contributor·

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• stream: make use of reverse parameter for changing byte endianness

  enhancement
  #2346·ozel opened Oct 8, 2025·

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  2

• build: efinix: efinity: hide excluded ios

  #2290·maass-hamburg opened Jul 23, 2025Contributor·

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  2

• Add RISC-V CLIC and CLINT interrupt controller support

  new-feature
  #2260·disdi opened Jun 15, 2025Contributor·

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  1

• Add option to specify a custom list of components in the setup script

  new-feature
  #2239·MarekPikula opened May 8, 2025·

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• copy picolibc to build folder, as it gets modified while building

  enhancement
  #2209·TuxCoder opened Mar 16, 2025·

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  1

• soc/integration: Add support for grouped regions

  enhancement
  #2194·cherrypiejam opened Mar 4, 2025·

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• Added preliminary support for riscv-steel processor.

  new-feature
  #2190·BMorgan1296 opened Feb 20, 2025·

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  3