fix sound & control sync

ericlewis · Sep 13, 2022 · 1b92b6e · 1b92b6e
1 parent 6f13911
commit 1b92b6e
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Showing 4 changed files with 7 additions and 7 deletions.
diff --git a/src/fpga/apf/build_id.mif b/src/fpga/apf/build_id.mif
@@ -10,7 +10,7 @@ CONTENT
 BEGIN
 
    0E0 : 20220913;
-   0E1 : 00095429;
-   0E2 : 82fdc294;
+   0E1 : 00104130;
+   0E2 : a95ae194;
 
 END;
diff --git a/src/fpga/core/core_top.v b/src/fpga/core/core_top.v
@@ -493,7 +493,7 @@ mf_pllbase mp1 (
   //
   // synchronize audio samples coming from the core
   wire	[31:0]	audgen_sampdata_s;
-  synch_3 #(.WIDTH(32)) s5(({1'b0, audio, 1'b0, audio}), audgen_sampdata_s, audgen_sclk);
+  synch_3 #(.WIDTH(32)) s5(({1'b0, audio[7:1], 1'b0, audio[7:1]}), audgen_sampdata_s, audgen_sclk);
   reg		[31:0]	audgen_sampshift;
   reg		[4:0]	audgen_lrck_cnt;
   reg				audgen_lrck;
@@ -601,15 +601,15 @@ synch_2 #(
 ) cont1_s (
   cont1_key,
   cont1_key_s,
-  clk_25
+  clk_6
 );
 
 synch_2 #(
   .WIDTH(16)
 ) cont2_s (
   cont2_key,
   cont2_key_s,
-  clk_25
+  clk_6
 );
 
 wire [7:0] BUTTON = {
@@ -632,9 +632,9 @@ reg [3:0] g2;
 reg [3:0] b2;
 
 always @(posedge clk_50) begin
-    r2 <= r;
+   r2 <= r;
 	g2 <= g;
-    b2 <= b;
+   b2 <= b;
 end
 
 wire [7:0] audio;

diff --git a/src/fpga/output_files/ap_core.rbf b/src/fpga/output_files/ap_core.rbf
diff --git a/src/fpga/output_files/ap_core.sof b/src/fpga/output_files/ap_core.sof