fix: wavy video

ericlewis · Oct 11, 2022 · bfb004c · bfb004c
1 parent 6947c5e
commit bfb004c
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Showing 16 changed files with 54 additions and 55 deletions.
diff --git a/dist/Cores/ericlewis.Asteroids/bitstream.rbf_r b/dist/Cores/ericlewis.Asteroids/bitstream.rbf_r
diff --git a/src/fpga/apf/build_id.mif b/src/fpga/apf/build_id.mif
@@ -10,7 +10,7 @@ CONTENT
 BEGIN
 
    0E0 : 20221011;
-   0E1 : 00152202;
-   0E2 : 882626ce;
+   0E1 : 00163114;
+   0E2 : 2a347c62;
 
 END;
diff --git a/src/fpga/core/core_top.v b/src/fpga/core/core_top.v
@@ -548,7 +548,6 @@ wire [24:0] ioctl_addr;
 wire  [7:0] ioctl_dout;
 
 data_loader #(
-    .ADDRESS_MASK_UPPER_4(0), 
     .WRITE_MEM_CLOCK_DELAY(4)
 ) rom_loader (
     .clk_74a(clk_74a),

diff --git a/src/fpga/core/mf_pllbase.qip b/src/fpga/core/mf_pllbase.qip
diff --git a/src/fpga/core/mf_pllbase.v b/src/fpga/core/mf_pllbase.v
@@ -63,7 +63,7 @@ endmodule
 // Retrieval info: 	<generic name="gui_pll_mode" value="Fractional-N PLL" />
 // Retrieval info: 	<generic name="gui_reference_clock_frequency" value="74.25" />
 // Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
-// Retrieval info: 	<generic name="gui_operation_mode" value="normal" />
+// Retrieval info: 	<generic name="gui_operation_mode" value="direct" />
 // Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
 // Retrieval info: 	<generic name="gui_fractional_cout" value="32" />
 // Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
@@ -83,7 +83,7 @@ endmodule
 // Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
 // Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
 // Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="25.175" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="25.0" />
 // Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
 // Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="276.740640 MHz" />
 // Retrieval info: 	<generic name="gui_ps_units1" value="degrees" />
@@ -110,7 +110,7 @@ endmodule
 // Retrieval info: 	<generic name="gui_actual_phase_shift3" value="225.0 deg" />
 // Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
 // Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="25.175" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="25.0" />
 // Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
 // Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
 // Retrieval info: 	<generic name="gui_ps_units4" value="ps" />

diff --git a/src/fpga/core/mf_pllbase/mf_pllbase_0002.qip b/src/fpga/core/mf_pllbase/mf_pllbase_0002.qip
@@ -1,4 +1,4 @@
-set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*"
 set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*"
 set_instance_assignment -name PLL_AUTO_RESET OFF -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*"
 set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*"
diff --git a/src/fpga/core/mf_pllbase/mf_pllbase_0002.v b/src/fpga/core/mf_pllbase/mf_pllbase_0002.v
@@ -29,21 +29,21 @@ module  mf_pllbase_0002(
 	altera_pll #(
 		.fractional_vco_multiplier("true"),
 		.reference_clock_frequency("74.25 MHz"),
-		.operation_mode("normal"),
+		.operation_mode("direct"),
 		.number_of_clocks(5),
-		.output_clock_frequency0("5.999999 MHz"),
+		.output_clock_frequency0("6.000000 MHz"),
 		.phase_shift0("0 ps"),
 		.duty_cycle0(50),
-		.output_clock_frequency1("25.173911 MHz"),
-		.phase_shift1("9931 ps"),
+		.output_clock_frequency1("25.000000 MHz"),
+		.phase_shift1("10000 ps"),
 		.duty_cycle1(50),
-		.output_clock_frequency2("50.347822 MHz"),
+		.output_clock_frequency2("50.000000 MHz"),
 		.phase_shift2("0 ps"),
 		.duty_cycle2(50),
-		.output_clock_frequency3("25.173910 MHz"),
+		.output_clock_frequency3("25.000000 MHz"),
 		.phase_shift3("0 ps"),
 		.duty_cycle3(50),
-		.output_clock_frequency4("25.173910 MHz"),
+		.output_clock_frequency4("25.000000 MHz"),
 		.phase_shift4("0 ps"),
 		.duty_cycle4(50),
 		.output_clock_frequency5("0 MHz"),

diff --git a/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl b/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 21.1 850 win32 2022.09.11.12:56:01
+# ACDS 21.1 850 win32 2022.10.11.16:30:49
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------

diff --git a/src/fpga/core/mf_pllbase_sim/cadence/ncsim_setup.sh b/src/fpga/core/mf_pllbase_sim/cadence/ncsim_setup.sh
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 21.1 850 win32 2022.09.11.12:56:01
+# ACDS 21.1 850 win32 2022.10.11.16:30:49
 
 # ----------------------------------------
 # ncsim - auto-generated simulation script
@@ -106,7 +106,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 21.1 850 win32 2022.09.11.12:56:01
+# ACDS 21.1 850 win32 2022.10.11.16:30:49
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="mf_pllbase"

diff --git a/src/fpga/core/mf_pllbase_sim/mentor/msim_setup.tcl b/src/fpga/core/mf_pllbase_sim/mentor/msim_setup.tcl
@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 21.1 850 win32 2022.09.11.12:56:01
+# ACDS 21.1 850 win32 2022.10.11.16:30:49
 
 # ----------------------------------------
 # Initialize variables

diff --git a/src/fpga/core/mf_pllbase_sim/mf_pllbase.vo b/src/fpga/core/mf_pllbase_sim/mf_pllbase.vo
@@ -234,9 +234,9 @@ module  mf_pllbase
 		mf_pllbase_altera_pll_altera_pll_i_2475.n_cnt_lo_div = 1,
 		mf_pllbase_altera_pll_altera_pll_i_2475.n_cnt_odd_div_duty_en = "false",
 		mf_pllbase_altera_pll_altera_pll_i_2475.number_of_clocks = 5,
-		mf_pllbase_altera_pll_altera_pll_i_2475.operation_mode = "normal",
-		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency0 = "5.999999 MHz",
-		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency1 = "25.173911 MHz",
+		mf_pllbase_altera_pll_altera_pll_i_2475.operation_mode = "direct",
+		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency0 = "6.000000 MHz",
+		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency1 = "25.000000 MHz",
 		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency10 = "0 MHz",
 		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency11 = "0 MHz",
 		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency12 = "0 MHz",
@@ -245,16 +245,16 @@ module  mf_pllbase
 		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency15 = "0 MHz",
 		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency16 = "0 MHz",
 		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency17 = "0 MHz",
-		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency2 = "50.347822 MHz",
-		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency3 = "25.173910 MHz",
-		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency4 = "25.173910 MHz",
+		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency2 = "50.000000 MHz",
+		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency3 = "25.000000 MHz",
+		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency4 = "25.000000 MHz",
 		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency5 = "0 MHz",
 		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency6 = "0 MHz",
 		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency7 = "0 MHz",
 		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency8 = "0 MHz",
 		mf_pllbase_altera_pll_altera_pll_i_2475.output_clock_frequency9 = "0 MHz",
 		mf_pllbase_altera_pll_altera_pll_i_2475.phase_shift0 = "0 ps",
-		mf_pllbase_altera_pll_altera_pll_i_2475.phase_shift1 = "9931 ps",
+		mf_pllbase_altera_pll_altera_pll_i_2475.phase_shift1 = "10000 ps",
 		mf_pllbase_altera_pll_altera_pll_i_2475.phase_shift10 = "0 ps",
 		mf_pllbase_altera_pll_altera_pll_i_2475.phase_shift11 = "0 ps",
 		mf_pllbase_altera_pll_altera_pll_i_2475.phase_shift12 = "0 ps",

diff --git a/src/fpga/core/mf_pllbase_sim/synopsys/vcs/vcs_setup.sh b/src/fpga/core/mf_pllbase_sim/synopsys/vcs/vcs_setup.sh
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 21.1 850 win32 2022.09.11.12:56:01
+# ACDS 21.1 850 win32 2022.10.11.16:30:49
 
 # ----------------------------------------
 # vcs - auto-generated simulation script
@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 21.1 850 win32 2022.09.11.12:56:01
+# ACDS 21.1 850 win32 2022.10.11.16:30:49
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="mf_pllbase"

diff --git a/src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/vcsmx_setup.sh b/src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/vcsmx_setup.sh
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 21.1 850 win32 2022.09.11.12:56:01
+# ACDS 21.1 850 win32 2022.10.11.16:30:49
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -107,7 +107,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 21.1 850 win32 2022.09.11.12:56:01
+# ACDS 21.1 850 win32 2022.10.11.16:30:49
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="mf_pllbase"

diff --git a/src/fpga/output_files/ap_core.rbf b/src/fpga/output_files/ap_core.rbf
diff --git a/src/fpga/output_files/ap_core.sof b/src/fpga/output_files/ap_core.sof
diff --git a/src/fpga/output_files/bitstream.rbf_r b/src/fpga/output_files/bitstream.rbf_r