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feat: dips
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@ericlewis
ericlewis committed Oct 11, 2022
1 parent 0da5f61 commit d8ad2f0
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Showing 16 changed files with 661 additions and 328 deletions.
Binary file modified dist/Cores/ericlewis.Asteroids/bitstream.rbf_r
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62 changes: 61 additions & 1 deletion dist/Cores/ericlewis.Asteroids/interact.json
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Original file line number Diff line number Diff line change
@@ -1,7 +1,67 @@
{
"interact": {
"magic": "APF_VER_1",
"variables": [],
"variables": [
{
"name": "Language",
"id": 1,
"type": "list",
"enabled": true,
"persist": true,
"address": "0x80000000",
"writeonly": true,
"defaultval": 0,
"options": [
{
"value": 0,
"name": "English"
},
{
"value": 1,
"name": "German"
},
{
"value": 2,
"name": "French"
},
{
"value": 3,
"name": "Spanish"
}
]
},
{
"name": "Ships",
"id": 2,
"type": "list",
"enabled": true,
"persist": true,
"address": "0x90000000",
"writeonly": true,
"defaultval": 0,
"options": [
{
"value": 0,
"name": "3"
},
{
"value": 1,
"name": "4"
}
]
},
{
"name": "Self-Test",
"id": 3,
"type": "check",
"enabled": true,
"persist": true,
"address": "0x10000000",
"writeonly": true,
"defaultval": 0,
"value": 1
}
],
"messages": []
}
}
14 changes: 8 additions & 6 deletions src/fpga/ap_core.qsf
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Expand Up @@ -738,7 +738,12 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

# end ENTITY(mf_pllbase_0002)
# ---------------------------
set_global_assignment -name VERILOG_FILE core/data_loader_8.v
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
set_global_assignment -name SYSTEMVERILOG_FILE core/data_loader.sv
set_global_assignment -name SYSTEMVERILOG_FILE core/sync_fifo.sv
set_global_assignment -name SYSTEMVERILOG_FILE core/sound_i2s.sv
set_global_assignment -name VHDL_FILE core/rtl/T65_Pack.vhd
set_global_assignment -name VHDL_FILE core/rtl/T65_MCode.vhd
set_global_assignment -name VHDL_FILE core/rtl/T65_ALU.vhd
Expand All @@ -759,8 +764,5 @@ set_global_assignment -name SIGNALTAP_FILE core/stp1.stp
set_global_assignment -name QIP_FILE core/mf_pllbase.qip
set_global_assignment -name SIP_FILE core/mf_pllbase.sip
set_global_assignment -name SOURCE_FILE db/ap_core.cmp.rdb
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
11 changes: 5 additions & 6 deletions src/fpga/apf/apf_top.v
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Expand Up @@ -280,10 +280,10 @@ mf_ddio_bidir_12 isclk(


// controller data (pad) controller.
wire [15:0] cont1_key;
wire [15:0] cont2_key;
wire [15:0] cont3_key;
wire [15:0] cont4_key;
wire [31:0] cont1_key;
wire [31:0] cont2_key;
wire [31:0] cont3_key;
wire [31:0] cont4_key;
wire [31:0] cont1_joy;
wire [31:0] cont2_joy;
wire [31:0] cont3_joy;
Expand Down Expand Up @@ -471,5 +471,4 @@ core_top ic (

);

endmodule

endmodule
6 changes: 3 additions & 3 deletions src/fpga/apf/build_id.mif
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Expand Up @@ -9,8 +9,8 @@ DATA_RADIX = HEX;
CONTENT
BEGIN

0E0 : 20220913;
0E1 : 00104130;
0E2 : a95ae194;
0E0 : 20221011;
0E1 : 00152202;
0E2 : 882626ce;

END;
8 changes: 2 additions & 6 deletions src/fpga/apf/common.v
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Expand Up @@ -8,11 +8,7 @@
// laws, including, but not limited to, U.S. copyright law. All rights are
// reserved. By using the APF code you are agreeing to the terms of the End User
// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula]
// and incorporated herein by reference. To the extent any use of the APF requires
// application of the MIT License or the GNU General Public License and terms of
// this APF Software License Agreement and EULA are inconsistent with such license,
// the applicable terms of the MIT License or the GNU General Public License, as
// applicable, will prevail.
// and incorporated herein by reference.

// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED
// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO,
Expand Down Expand Up @@ -153,4 +149,4 @@ always @(posedge b_clk) begin
b_dout <= mem[b_addr];
end

endmodule
endmodule
2 changes: 1 addition & 1 deletion src/fpga/apf/io_bridge_peripheral.v
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Expand Up @@ -331,4 +331,4 @@ always @(posedge phy_spiclk or posedge phy_spiss) begin
end
end

endmodule
endmodule
18 changes: 9 additions & 9 deletions src/fpga/apf/io_pad_controller.v
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Expand Up @@ -45,10 +45,10 @@ input wire reset_n,

inout reg pad_1wire,

output reg [15:0] cont1_key,
output reg [15:0] cont2_key,
output reg [15:0] cont3_key,
output reg [15:0] cont4_key,
output reg [31:0] cont1_key,
output reg [31:0] cont2_key,
output reg [31:0] cont3_key,
output reg [31:0] cont4_key,
output reg [31:0] cont1_joy,
output reg [31:0] cont2_joy,
output reg [31:0] cont3_joy,
Expand Down Expand Up @@ -140,19 +140,19 @@ always @(posedge clk) begin
if(rx_word_done) begin
cnt <= cnt + 1'b1;
case(cnt)
0: cont1_key <= rx_word[15:0];
0: cont1_key <= rx_word;
1: cont1_joy <= rx_word;
2: cont1_trig <= rx_word[15:0];

3: cont2_key <= rx_word[15:0];
3: cont2_key <= rx_word;
4: cont2_joy <= rx_word;
5: cont2_trig <= rx_word[15:0];

6: cont3_key <= rx_word[15:0];
6: cont3_key <= rx_word;
7: cont3_joy <= rx_word;
8: cont3_trig <= rx_word[15:0];

9: cont4_key <= rx_word[15:0];
9: cont4_key <= rx_word;
10: cont4_joy <= rx_word;
11: begin
cont4_trig <= rx_word[15:0];
Expand Down Expand Up @@ -325,4 +325,4 @@ always @(posedge clk) begin
if(~reset_n_s | ~reset_tr_n) tr_state <= TR_IDLE;
end

endmodule
endmodule
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