Add IObundle open-source cores (Cache, Ethernet, UART) #33
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This PR adds three open-source IP cores developed by IObundle, Lda as FuseSoC cores.
Included cores:
IOb-Cache – https://github.com/IObundle/iob-cache
High-performance, configurable Verilog cache core, already used in multiple SoC designs and described in the IOb-Cache publication.
IOb-Eth – https://github.com/IObundle/iob-eth
Ethernet MAC core that provides raw Ethernet (layer 2) communication and a C driver; currently functional but with some features still under development.
IOb-UART16550 – https://github.com/IObundle/iob-uart16550
16550-compatible UART core derived from the OpenCores design, adapted to the IOb interface instead of Wishbone and improved for better integration with IObundle’s SoC infrastructure.