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garvkuiuc/README.md

Garv Khera Computer Engineering @ UIUC | Systems, Architecture, & Digital Design

I am a Computer Engineering student at the University of Illinois Urbana-Champaign specializing in the boundary between hardware and software. My experience ranges from developing Unix-style OS kernels to RTL design for custom processors and ASIC/FPGA verification. I focus on building robust, low-level infrastructure, whether that is optimizing a VirtIO driver, managing demand-paged virtual memory, or ensuring deterministic timing in hardware pipelines.

Technical Depth

Low-Level Systems: Experienced in C and RISC-V for kernel-level programming. Comfortable navigating complex build systems (Makefiles), tracing linker errors, and managing memory/pointer behavior in performance-critical environments.

Digital Design & RTL: Proficient in SystemVerilog and Verilog for processor design and FPGA implementation. Skilled in the full design flow: from writing control FSMs and datapaths to cycle-accurate simulation and physical hardware deployment.

Verification & Tooling: Use of industry-standard tools like Xcellium, Vivado, and Genus for hardware validation. I also leverage Python to build automated testing pipelines and validation scripts for complex workflows.

Key Projects

RISC-V Unix-Style Operating System Kernel

  • Developed a ~15k LOC kernel with system calls, user processes, and preemptive scheduling.
  • Implemented virtual memory with demand paging, managing page faults and process memory mapping.
  • Engineered VirtIO block device drivers supporting buffered I/O with PLIC-driven interrupts.
  • Built a custom filesystem (KTFS) and a shell supporting pipes, redirection, and concurrent processes.

16-bit SLC-3 Processor RTL Design

  • Designed a processor featuring a full fetch-decode-execute memory-writeback pipeline in SystemVerilog.
  • Built 20+ RTL modules including the ALU, control FSM, register file, and synchronous memory.
  • Verified correctness via cycle-accurate simulation across 100+ programs before FPGA deployment.

Real-Time FPGA Game System

  • Architected a hardware pipeline for VGA output (640x480 @ 60 Hz) with single-cycle deterministic timing.
  • Coordinated HW/SW co-design by integrating a MicroBlaze processor for PS/2 input and control logic.

Professional Experience

  • IBM (Brand Technical Specialist Intern): Authored a 35-page report on OpenShift/Kubernetes architecture and delivered 12+ technical demos for Cloud Pak for Data.
  • Mercor (Software Engineer): Built automated evaluation pipelines to validate model responses across C, C++, and Python.
  • Technology Dynamics (Software Engineering Intern): Fine-tuned Python-based models to improve speech-to-text accuracy and built RAG chatbots.

Connect

LinkedIn: linkedin.com/in/garv-khera-435287254

Email: garvkhera@gmail.com

Pinned Loading

  1. riscv-unix-kernel riscv-unix-kernel Public

    A Unix-style OS kernel for RISC-V featuring virtual memory, file systems, preemptive scheduling, shells, and VirtIO drivers.

    C 1

  2. slc3-16bit-processor-rtl slc3-16bit-processor-rtl Public

    An RTL implementation of the SLC-3 (Simplified Little Computer 3), a 16-bit Von Neumann microprocessor. Features a 16-bit ISA, ALU, register file, and FSM-based control unit for FPGA synthesis.

    SystemVerilog 1

  3. fpga-head-soccer-soc fpga-head-soccer-soc Public

    Build a real-time Head Soccer clone featuring a MicroBlaze SoC integrated with high-performance SystemVerilog accelerators. Optimized for 60FPS VGA rendering and hardware-driven physics.

    SystemVerilog 2

  4. ai_chatbot ai_chatbot Public

    Forked from pyanda2/ai_chatbot

    Python