Update to Amaranth 0.5

applets/clear_endpoint_halt_test.py

@@ -31,7 +31,7 @@
 COUNTER_MAX = 251
 GET_OUT_COUNTER_VALID = 0
 
-out_counter_valid = Signal(reset=1)
+out_counter_valid = Signal(init=1)
 
 class VendorRequestHandler(ControlRequestHandler):
 
@@ -137,7 +137,7 @@ def elaborate(self, platform):
                 m.d.usb += in_counter.eq(0)
 
         # Expect a counter on the OUT endpoint, and verify that it is contiguous.
-        prev_out_counter = Signal(8, reset=COUNTER_MAX)
+        prev_out_counter = Signal(8, init=COUNTER_MAX)
         with m.If(stream_out_ep.stream.valid):
             out_counter = stream_out_ep.stream.payload
             counter_increase = out_counter == (prev_out_counter + 1)

applets/hyperram_diagnostic.py

@@ -69,7 +69,7 @@ def elaborate(self, platform):
         m.submodules.registers = registers
 
         psram_address = registers.add_register(REGISTER_RAM_ADDR)
-        read_length   = registers.add_register(REGISTER_RAM_READ_LENGTH, reset=1)
+        read_length   = registers.add_register(REGISTER_RAM_READ_LENGTH, init=1)
 
         m.submodules.read_fifo  = read_fifo  = SyncFIFO(width=REG_WIDTH, depth=32)
         m.submodules.write_fifo = write_fifo = SyncFIFO(width=REG_WIDTH, depth=32)

examples/usb/stress_test_device.py

@@ -60,7 +60,7 @@ def elaborate(self, platform):
         tx        = interface.tx
 
         # Counter that stores how many bytes we have left to send.
-        bytes_to_send = Signal(range(0, self._max_packet_size + 1), reset=0)
+        bytes_to_send = Signal(range(0, self._max_packet_size + 1), init=0)
 
         # True iff we're the active endpoint.
         endpoint_selected = \

luna/gateware/architecture/car.py

@@ -56,7 +56,7 @@ def elaborate(self, platform):
         cycles_in_reset = Signal(range(0, self.reset_length_cycles))
 
         reset_state = 'RESETTING' if self.power_on_reset else 'IDLE'
-        with m.FSM(reset=reset_state, domain='sync') as fsm:
+        with m.FSM(init=reset_state, domain='sync') as fsm:
 
             # Drive the PHY reset whenever we're in the RESETTING cycle.
             m.d.comb += [

luna/gateware/debug/ila.py

@@ -13,17 +13,18 @@
 import tempfile
 import subprocess
 
-from abc               import ABCMeta, abstractmethod
+from abc                 import ABCMeta, abstractmethod
 
-from amaranth          import Signal, Module, Cat, Elaboratable, Memory, ClockDomain, DomainRenamer
-from amaranth.lib.cdc  import FFSynchronizer
-from amaranth.lib.fifo import AsyncFIFOBuffered
-from vcd               import VCDWriter
-from vcd.gtkw          import GTKWSave
+from amaranth            import Cat, DomainRenamer, Elaboratable, Module, Shape, Signal
+from amaranth.lib.cdc    import FFSynchronizer
+from amaranth.lib.fifo   import AsyncFIFOBuffered
+from amaranth.lib.memory import Memory
+from vcd                 import VCDWriter
+from vcd.gtkw            import GTKWSave
 
-from ..stream          import StreamInterface
-from ..interface.uart  import UARTMultibyteTransmitter
-from ..interface.spi   import SPIDeviceInterface, SPIBus
+from ..stream            import StreamInterface
+from ..interface.uart    import UARTMultibyteTransmitter
+from ..interface.spi     import SPIDeviceInterface, SPIBus
 
 
 class IntegratedLogicAnalyzer(Elaboratable):
@@ -77,7 +78,7 @@ def __init__(self, *, signals, sample_depth, domain="sync", sample_rate=60e6, sa
         #
         # Create a backing store for our samples.
         #
-        self.mem = Memory(width=self.sample_width, depth=sample_depth, name="ila_buffer")
+        self.mem = Memory(shape=Shape(self.sample_width), depth=sample_depth, init=[])
 
 
         #
@@ -97,7 +98,7 @@ def elaborate(self, platform):
         # Memory ports.
         write_port = self.mem.write_port()
         read_port  = self.mem.read_port(domain="sync")
-        m.submodules += [write_port, read_port]
+        m.submodules['ila_buffer'] = self.mem
 
         # If necessary, create synchronized versions of the relevant signals.
         if self.samples_pretrigger >= 2:
@@ -454,7 +455,7 @@ def elaborate(self, platform):
             # SENDING -- we now have a valid buffer of samples to send up to the host;
             # we'll transmit them over our stream interface.
             with m.State("SENDING"):
-                data_valid = Signal(reset=1)
+                data_valid = Signal(init=1)
                 m.d.comb += [
                     # While we're sending, we're always providing valid data to the UART.
                     in_domain_stream.valid  .eq(data_valid),

luna/gateware/interface/flash.py

@@ -103,8 +103,8 @@ def elaborate(self, platform):
         ]
 
         # Output shift register and bit counter
-        shreg_o = Signal(8, reset=self.READ_UID)
-        count_o = Signal(range(128), reset=8*(1+4+8)-1)  # bytes: 1 opcode, 4 padding, 8 id
+        shreg_o = Signal(8, init=self.READ_UID)
+        count_o = Signal(range(128), init=8*(1+4+8)-1)  # bytes: 1 opcode, 4 padding, 8 id
 
         with m.FSM(domain=self._domain):
 

luna/gateware/interface/gateware_phy/receiver.py

@@ -439,7 +439,7 @@ def __init__(self):
         # pass all of the outputs through a pipe stage
         self.o_data = Signal()
         self.o_error = Signal()
-        self.o_stall = Signal(reset=1)
+        self.o_stall = Signal(init=1)
 
 
     def elaborate(self, platform):
@@ -536,7 +536,7 @@ def elaborate(self, platform):
 
         # Instead of using a counter, we will use a sentinel bit in the shift
         # register to indicate when it is full.
-        shift_reg = Signal(width+1, reset=0b1)
+        shift_reg = Signal(width+1, init=0b1)
 
         m.d.comb += self.o_data.eq(shift_reg[0:width])
         m.d.usb_io += self.o_put.eq(shift_reg[width-1] & ~shift_reg[width] & self.i_valid),
@@ -562,8 +562,8 @@ def __init__(self):
         self.o_bit_strobe = Signal()
 
         # Reset state is J
-        self.i_usbp = Signal(reset=1)
-        self.i_usbn = Signal(reset=0)
+        self.i_usbp = Signal(init=1)
+        self.i_usbn = Signal(init=0)
 
         self.o_data_strobe = Signal()
         self.o_data_payload = Signal(8)

luna/gateware/interface/gateware_phy/transmitter.py

@@ -94,7 +94,7 @@ def elaborate(self, platform):
         m = Module()
 
         shifter = Signal(self._width)
-        pos = Signal(self._width, reset=0b1)
+        pos = Signal(self._width, init=0b1)
 
 
         with m.If(self.i_enable):

luna/gateware/interface/i2c.py

@@ -231,9 +231,9 @@ def __init__(self, pads):
         self.sda_t  = pads.sda_t if hasattr(pads, "sda_t") else pads.sda
 
         self.scl_i  = Signal()
-        self.scl_o  = Signal(reset=1)
+        self.scl_o  = Signal(init=1)
         self.sda_i  = Signal()
-        self.sda_o  = Signal(reset=1)
+        self.sda_o  = Signal(init=1)
 
         self.sample = Signal(name="bus_sample")
         self.setup  = Signal(name="bus_setup")
@@ -248,15 +248,15 @@ def elaborate(self, platform):
             self.sda_t.o  .eq(0),
             self.sda_t.oe .eq(~self.sda_o),
         ]
-        m.submodules += FFSynchronizer(self.sda_t.i, self.sda_i, reset=1)
+        m.submodules += FFSynchronizer(self.sda_t.i, self.sda_i, init=1)
 
         # But the SCL line does not need to: only if we want to support clock stretching
         if hasattr(self.scl_t, "oe"):
             m.d.comb += [
                 self.scl_t.o  .eq(0),
                 self.scl_t.oe .eq(~self.scl_o),
             ]
-            m.submodules += FFSynchronizer(self.scl_t.i, self.scl_i, reset=1)
+            m.submodules += FFSynchronizer(self.scl_t.i, self.scl_i, init=1)
         else:
             # SCL output only
             m.d.comb += [
@@ -265,8 +265,8 @@ def elaborate(self, platform):
             ]
 
         # Additional signals for bus state detection
-        scl_r = Signal(reset=1)
-        sda_r = Signal(reset=1)
+        scl_r = Signal(init=1)
+        sda_r = Signal(init=1)
         m.d.sync += [
             scl_r.eq(self.scl_i),
             sda_r.eq(self.sda_i),
@@ -327,7 +327,7 @@ def __init__(self, pads, period_cyc, clk_stretch=True):
         self.period_cyc  = int(period_cyc)
         self.clk_stretch = clk_stretch
 
-        self.busy   = Signal(reset=1)
+        self.busy   = Signal(init=1)
         self.start  = Signal()
         self.stop   = Signal()
         self.read   = Signal()

luna/gateware/interface/jtag.py

@@ -200,8 +200,8 @@ def elaborate(self, platform):
         #
         ir_size              = self.command_size + 1
         dr_size              = self.word_size + 1
-        instruction_register = Signal(ir_size, reset=(2 ** ir_size - 1))
-        data_register        = Signal(dr_size, reset=(2 ** dr_size - 1))
+        instruction_register = Signal(ir_size, init=(2 ** ir_size - 1))
+        data_register        = Signal(dr_size, init=(2 ** dr_size - 1))
 
         #
         # JTAG interface.

luna/gateware/interface/serdes_phy/ecp5.py

@@ -445,10 +445,10 @@ def __init__(self):
         self.rx_coding_err  = Signal()
 
         # Reset out.
-        self.tx_pll_reset   = Signal(reset=1)
-        self.tx_pcs_reset   = Signal(reset=1)
-        self.rx_cdr_reset   = Signal(reset=1)
-        self.rx_pcs_reset   = Signal(reset=1)
+        self.tx_pll_reset   = Signal(init=1)
+        self.tx_pcs_reset   = Signal(init=1)
+        self.rx_cdr_reset   = Signal(init=1)
+        self.rx_pcs_reset   = Signal(init=1)
 
         # Status out.
         self.tx_pcs_ready   = Signal()

luna/gateware/interface/serdes_phy/xc7.py

@@ -113,13 +113,13 @@ def elaborate(self, platform):
 class DRPFieldController(Elaboratable):
     """ Gateware that atomically updates part of a word via DRP. """
 
-    def __init__(self, *, addr: int, bits: slice, reset=0):
+    def __init__(self, *, addr: int, bits: slice, init=0):
         self._addr = addr
         self._bits = bits
 
         self.drp = DRPInterface()
 
-        self.value = Signal(bits.stop - bits.start, reset=reset)
+        self.value = Signal(bits.stop - bits.start, init=reset)
 
 
     def elaborate(self, platform):
@@ -193,7 +193,7 @@ def elaborate(self, platform):
         timer  = Signal(range(cycles))
 
         # Defer reset immediately after configuration; and never again, even if our domain is reset.
-        defer  = Signal(reset=1, reset_less=True)
+        defer  = Signal(init=1, reset_less=True)
 
         with m.If(defer):
             m.d.ss += timer.eq(timer + 1)

luna/gateware/interface/serdes_phy/xc7_gtp.py

@@ -282,7 +282,7 @@ def elaborate(self, platform):
         m.submodules += FFSynchronizer(self.rx_termination, rx_termination, o_domain="ss")
 
         m.submodules.rx_term = rx_term = DRPFieldController(
-            addr=0x0011, bits=slice(4, 6), reset=0b10) # RX_CM_SEL
+            addr=0x0011, bits=slice(4, 6), init=0b10) # RX_CM_SEL
         m.d.comb += [
             rx_term.value.eq(Mux(rx_termination,
                                  0b11,    # Programmable

luna/gateware/interface/serdes_phy/xc7_gtx.py

@@ -388,7 +388,7 @@ def elaborate(self, platform):
         m.submodules += FFSynchronizer(self.rx_termination, rx_termination, o_domain="ss")
 
         m.submodules.rx_term = rx_term = DRPFieldController(
-            addr=0x0011, bits=slice(4, 6), reset=0b10) # RX_CM_SEL
+            addr=0x0011, bits=slice(4, 6), init=0b10) # RX_CM_SEL
         m.d.comb += [
             rx_term.value.eq(Mux(self.rx_termination,
                                  0b11,    # Programmable

luna/gateware/interface/spi.py

@@ -102,7 +102,7 @@ def elaborate(self, platform):
 
         # We'll use separate buffers for transmit and receive,
         # as this makes the code a little more readable.
-        bit_count    = Signal(range(0, self.word_size), reset=0)
+        bit_count    = Signal(range(0, self.word_size), init=0)
         current_tx   = Signal.like(self.word_out)
         current_rx   = Signal.like(self.word_in)
 
@@ -537,7 +537,7 @@ def add_read_only_register(self, address, *, read, read_strobe=None):
 
 
     def add_register(self, address, *, value_signal=None, size=None, name=None, read_strobe=None,
-        write_strobe=None, reset=0):
+        write_strobe=None, init=0):
         """ Adds a standard, memory-backed register.
 
             Parameters:
@@ -561,7 +561,7 @@ def add_register(self, address, *, value_signal=None, size=None, name=None, read
         # Generate a backing store for the register, if we don't already have one.
         if value_signal is None:
             size = self.register_size if (size is None) else size
-            value_signal = Signal(size, name=name, reset=reset)
+            value_signal = Signal(size, name=name, init=init)
 
         # If we don't have a write strobe signal, create an internal one.
         if write_strobe is None:

luna/gateware/interface/uart.py

@@ -49,7 +49,7 @@ def __init__(self, *, divisor):
         #
         # I/O port
         #
-        self.tx              = Signal(reset=1)
+        self.tx              = Signal(init=1)
         self.driving         = Signal()
         self.stream          = StreamInterface()
 
@@ -168,7 +168,7 @@ def __init__(self, *, byte_width, divisor):
         #
         # I/O port
         #
-        self.tx              = Signal(reset=1)
+        self.tx              = Signal(init=1)
         self.stream          = StreamInterface(payload_width=byte_width * 8)
 
         self.idle            = Signal()

luna/gateware/interface/ulpi.py

@@ -397,22 +397,22 @@ def __init__(self, *, register_window, own_register_window=False):
         # I/O port
         #
         self.bus_idle      = Signal()
-        self.xcvr_select   = Signal(2, reset=0b01)
+        self.xcvr_select   = Signal(2, init=0b01)
         self.term_select   = Signal()
         self.op_mode       = Signal(2)
         self.suspend       = Signal()
 
         self.id_pullup     = Signal()
-        self.dp_pulldown   = Signal(reset=1)
-        self.dm_pulldown   = Signal(reset=1)
+        self.dp_pulldown   = Signal(init=1)
+        self.dm_pulldown   = Signal(init=1)
 
         self.chrg_vbus     = Signal()
         self.dischrg_vbus  = Signal()
 
         self.busy          = Signal()
 
         # Extra/non-UTMI properties.
-        self.use_external_vbus_indicator = Signal(reset=1)
+        self.use_external_vbus_indicator = Signal(init=1)
 
         #
         # Internal variables.
@@ -432,7 +432,7 @@ def add_composite_register(self, m, address, value, *, reset_value=0):
                         -- of the given register; allowing us to avoid an initial write.
         """
 
-        current_register_value = Signal(8, reset=reset_value, name=f"current_register_value_{address:02x}")
+        current_register_value = Signal(8, init=reset_value, name=f"current_register_value_{address:02x}")
 
         # Create internal signals that request register updates.
         write_requested = Signal(name=f"write_requested_{address:02x}")

luna/gateware/memory.py

@@ -8,7 +8,8 @@
 This module contains definitions of memory units that work well for USB applications.
 """
 
-from amaranth import Elaboratable, Module, Signal, Memory
+from amaranth import Elaboratable, Module, Shape, Signal
+from amaranth.lib.memory import Memory
 from amaranth.hdl.xfrm import DomainRenamer
 
 
@@ -108,9 +109,9 @@ def elaborate(self, platform):
         #
         # Core internal "backing store".
         #
-        memory = Memory(width=self.width, depth=self.depth + 1, name=self.name)
-        m.submodules.read_port  = read_port  = memory.read_port()
-        m.submodules.write_port = write_port = memory.write_port()
+        m.submodules[self.name] = memory = Memory(shape=Shape(self.width), depth=self.depth + 1, init=[])
+        read_port = memory.read_port()
+        write_port = memory.write_port()
 
         # Always connect up our memory's data/en ports to ours.
         m.d.comb += [

luna/gateware/stream/generator.py

@@ -6,8 +6,9 @@
 
 """ Stream generators. """
 
-from amaranth     import *
-from .            import StreamInterface
+from amaranth            import Array, Const, DomainRenamer, Elaboratable, Module, Shape, Signal
+from amaranth.lib.memory import Memory
+from .                   import StreamInterface
 
 
 class ConstantStreamGenerator(Elaboratable):
@@ -153,8 +154,8 @@ def elaborate(self, platform):
         data_initializer, valid_bits_last_word = self._get_initializer_value()
         data_length = len(data_initializer)
 
-        rom = Memory(width=self._data_width, depth=data_length, init=data_initializer)
-        m.submodules.rom_read_port = rom_read_port = rom.read_port(transparent=False)
+        m.submodules.rom = rom = Memory(shape=Shape(self._data_width), depth=data_length, init=data_initializer)
+        rom_read_port = rom.read_port()
 
         if self._max_length_width:
             # Register maximum length, to improve timing.