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VHDL parser from andres manelli's fork for entity parsing support #4

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Merged
merged 6 commits into from
Nov 29, 2021
Merged

VHDL parser from andres manelli's fork for entity parsing support #4

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8278098
VHDL parser from andres manelli's fork for more entity parsing support
Oct 24, 2021
c2fcf2b
Andres Manelli hotfix for type parsing in architectures
Nov 18, 2021
32c8722
Replaced single quote docstrings with double quotes
Nov 28, 2021
06c8b29
Reformatted code with PyCharm
Nov 28, 2021
37de2fb
VHDL documentation parser in single quotes wasn't complained about
Nov 28, 2021
0c7e333
Removed python 2 style class declaration
Nov 28, 2021
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6 changes: 3 additions & 3 deletions hdlparse/verilog_parser.py
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Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,7 @@
VerilogLexer = MiniLexer(verilog_tokens)


class VerilogObject(object):
class VerilogObject:
"""Base class for parsed Verilog objects"""

def __init__(self, name, desc=None):
Expand All @@ -68,7 +68,7 @@ def __init__(self, name, desc=None):
self.desc = [] if desc is None else desc


class VerilogParameter(object):
class VerilogParameter:
"""Parameter and port to a module"""

def __init__(self, name, mode=None, data_type=None, default_value=None, desc=None):
Expand Down Expand Up @@ -229,7 +229,7 @@ def is_verilog(fname):
return os.path.splitext(fname)[1].lower() in ('.vlog', '.v')


class VerilogExtractor(object):
class VerilogExtractor:
"""Utility class that caches parsed objects"""

def __init__(self):
Expand Down
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