cleaning up.

src/main/scala/ee/hrzn/chryse/platform/ice40/ICE40Top.scala

@@ -18,8 +18,6 @@ class ICE40Top[Top <: Module](
     platform: BoardPlatform[_ <: BoardResources],
     genTop: => Top,
 ) extends ChryseModule {
-  import platform.resources.clock.Implicits._
-
   override def desiredName = "ice40top"
 
   val clki = Wire(Clock())

src/main/scala/ee/hrzn/chryse/platform/resource/Base.scala

@@ -1,19 +1,22 @@
 package ee.hrzn.chryse.platform.resource
 
 import chisel3._
+import chisel3.experimental.dataview._
 
-trait Base[HW <: Data] {
+import scala.language.implicitConversions
+
+abstract class Base[HW <: Data](gen: => HW) {
   final private[chryse] var pinId: Option[Pin]   = None
   final private[chryse] var name: Option[String] = None
 
-  // Should return Input/Output Chisel datatype.
-  private[chryse] def makeIo(): HW
+  // Should return Chisel datatype.
+  private[chryse] def makeIo(): HW = gen
 
   final private[chryse] var ioInst: Option[InstSides[HW]] = None
 
-  /* Instantiate an IO in the module at the point of connection. These will be
-   * connected by the platform toplevel (which implies they can only be used in
-   * the user toplevel). */
+  /* Instantiate an IO in the module at the point of connecting to this
+   * resource. These will be connected to in turn by the platform toplevel
+   * (which implies they can only be used in the user toplevel). */
   private[chryse] def ioInstOrMake(): InstSides[HW] = {
     ioInst match {
       case Some(r) => r
@@ -28,6 +31,25 @@ trait Base[HW <: Data] {
     pinId = Some(id)
     this
   }
+
+  object Implicits {
+    implicit val BaseProduct: DataProduct[Base[HW]] =
+      new DataProduct[Base[HW]] {
+        def dataIterator(
+            res: Base[HW],
+            path: String,
+        ): Iterator[(Data, String)] =
+          List(res.ioInst.get.user -> path).iterator
+      }
+
+    implicit def view: DataView[Base[HW], HW] =
+      DataView(res => gen, _.ioInstOrMake().user -> _)
+
+    implicit def Base2HW(res: Base[HW]): HW =
+      res.viewAs[HW]
+  }
 }
 
 case class InstSides[HW](user: HW, top: HW)
+
+object BaseBool extends Base[Bool](Bool()) {}

src/main/scala/ee/hrzn/chryse/platform/resource/BaseIn.scala

@@ -1,27 +1,7 @@
 package ee.hrzn.chryse.platform.resource
 
 import chisel3._
-import chisel3.experimental.dataview._
 
-import scala.language.implicitConversions
-
-class BaseIn[HW <: Data](gen: => HW) extends Base[HW] {
-  private[chryse] def makeIo(): HW = Input(gen)
-
-  object Implicits {
-    implicit val BaseInProduct: DataProduct[BaseIn[HW]] =
-      new DataProduct[BaseIn[HW]] {
-        def dataIterator(
-            res: BaseIn[HW],
-            path: String,
-        ): Iterator[(Data, String)] =
-          List(res.ioInst.get.user -> path).iterator
-      }
-
-    implicit def view: DataView[BaseIn[HW], HW] =
-      DataView(res => gen, _.ioInstOrMake().user -> _)
-
-    implicit def BaseIn2HW(res: BaseIn[HW]): HW =
-      res.viewAs[HW]
-  }
+class BaseIn[HW <: Data](gen: => HW) extends Base[HW](gen) {
+  override private[chryse] def makeIo(): HW = Input(gen)
 }

src/main/scala/ee/hrzn/chryse/platform/resource/BaseOut.scala

@@ -1,27 +1,7 @@
 package ee.hrzn.chryse.platform.resource
 
 import chisel3._
-import chisel3.experimental.dataview._
 
-import scala.language.implicitConversions
-
-class BaseOut[HW <: Data](gen: => HW) extends Base[HW] {
-  private[chryse] def makeIo(): HW = Output(gen)
-
-  object Implicits {
-    implicit val BaseOutProduct: DataProduct[BaseOut[HW]] =
-      new DataProduct[BaseOut[HW]] {
-        def dataIterator(
-            res: BaseOut[HW],
-            path: String,
-        ): Iterator[(Data, String)] =
-          List(res.ioInst.get.user -> path).iterator
-      }
-
-    implicit def view: DataView[BaseOut[HW], HW] =
-      DataView(res => gen, _.ioInstOrMake().user -> _)
-
-    implicit def BaseOut2HW(res: BaseOut[HW]): HW =
-      res.viewAs[HW]
-  }
+class BaseOut[HW <: Data](gen: => HW) extends Base[HW](gen) {
+  override private[chryse] def makeIo(): HW = Output(gen)
 }

src/main/scala/ee/hrzn/chryse/platform/resource/InOut.scala

@@ -3,9 +3,7 @@ package ee.hrzn.chryse.platform.resource
 import chisel3._
 import chisel3.experimental.Analog
 
-class InOut extends Base[Analog] {
-  private[chryse] def makeIo(): Analog = Analog(1.W)
-}
+class InOut extends Base[Analog](Analog(1.W)) {}
 
 object InOut {
   def apply() = new InOut

src/test/scala/ee/hrzn/chryse/platform/BoardResourcesSpec.scala

@@ -6,8 +6,7 @@ import ee.hrzn.chryse.ChryseModule
 import ee.hrzn.chryse.chisel.BuilderContext
 import ee.hrzn.chryse.platform.ice40.ICE40Top
 import ee.hrzn.chryse.platform.ice40.IceBreakerPlatform
-import ee.hrzn.chryse.platform.resource.BaseInBool.Implicits._
-import ee.hrzn.chryse.platform.resource.BaseOutBool.Implicits._
+import ee.hrzn.chryse.platform.resource.BaseBool.Implicits._
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should._
 
@@ -28,24 +27,31 @@ class BoardResourcesSpec extends AnyFlatSpec with Matchers {
     )
   }
 
-  it should "invert inputs as requested" in {
+  it should "invert inputs as requested and use the correct top-level IO names" in {
     val plat             = IceBreakerPlatform()
     var top: ICE40Top[_] = null
-    val rtl = ChiselStage.emitSystemVerilog {
-      top = plat(new InversionTop(_))
-      top
-    }
+    val rtl = ChiselStage.emitSystemVerilog(
+      {
+        top = plat(new InversionTop(_))
+        top
+      },
+      firtoolOpts = Array("-strip-debug-info"),
+    )
     top.lastPCF.get.linesIterator.toList.sorted.mkString("\n") should be(
       """set_io clock 35
         |set_io ledg 37
         |set_io uart_tx 9
         |set_io ubtn 10""".stripMargin,
     )
-    // XXX: we aren't generating input names correctly. (¿Sometimes?)
-    // Test for this.
     rtl should include("ledg_int = view__ubtn_int")
     (rtl should not).include("uart_tx_int = view__ubtn_int")
     rtl should include("uart_tx_int = ~view__ubtn_int")
+
+    // HACK: this is brittle. Parse the Verilog or something.
+    "\\s+".r
+      .replaceAllIn(rtl, " ") should include(
+      "module ice40top( input clock, ubtn, output uart_tx, ledg );",
+    )
   }
 }
 
@@ -60,6 +66,6 @@ class InversionTop(platform: Platform) extends Module {
   // User button is inverted.
   // UART isn't inverted.
   plat.resources.uart_tx := plat.resources.ubtn
-  // LED isn't inverted.
+  // LED is inverted.
   plat.resources.ledg := plat.resources.ubtn
 }