Feature request: add UDP support

[rhanqtl]

Support for SystemVerilog User-Defined Primitives (UDPs) is currently missing in CIRCT. Although obsolete for frontend RTL design, UDPs are still ubiquitous in gate-level netlists and foundry-provided simulation models.

Adding UDP support will significantly broaden CIRCT's real-world applicability in the following scenarios:

1. Gate-Level Netlist Processing: Allows frontends (like Moore or slang-based parsers) to successfully ingest and lower post-synthesis netlists without choking on primitive definitions.
2. ASIC-to-FPGA Prototyping: Facilitates the translation, mapping, or black-boxing of ASIC cell library models containing combinational/sequential UDP tables into FPGA-compatible IR.
3. Ecosystem Interoperability: Enhances CIRCT's readiness for formal verification and physical design automation tools that interact directly with commercial PDKs.

I'd like to work on this if possible.