// Generated by CIRCT firtool-1.81.1-18-g6aa871500

// Users can define 'STOP_COND' to add an extra gate to stop conditions.
`ifndef STOP_COND_
  `ifdef STOP_COND
    `define STOP_COND_ (`STOP_COND)
  `else  // STOP_COND
    `define STOP_COND_ 1
  `endif // STOP_COND
`endif // not def STOP_COND_

// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing.
`ifndef ASSERT_VERBOSE_COND_
  `ifdef ASSERT_VERBOSE_COND
    `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND)
  `else  // ASSERT_VERBOSE_COND
    `define ASSERT_VERBOSE_COND_ 1
  `endif // ASSERT_VERBOSE_COND
`endif // not def ASSERT_VERBOSE_COND_
module Foo_A(
  input [1:0] a,
              b,
  input       clock
);

  `ifndef SYNTHESIS
    always @(posedge clock) begin
      if (a != b) begin
        if (`ASSERT_VERBOSE_COND_)
          $error("bar");
        if (`STOP_COND_)
          $fatal;
      end
    end // always @(posedge)
  `endif // not def SYNTHESIS
endmodule

module Foo(
  input        clock,
  input  [1:0] a,
  output [1:0] c
);

  assign c = a;
endmodule


// ----- 8< ----- FILE "layers_Foo_A.sv" ----- 8< -----

// Generated by CIRCT firtool-1.81.1-18-g6aa871500
`ifndef layers_Foo_A
`define layers_Foo_A
bind Foo Foo_A a_0 (
  .a     (a),
  .b     (a),
  .clock (clock)
);
`endif // layers_Foo_A

// Generated by CIRCT firtool-1.81.1-18-g6aa871500
module Foo(
  input        clock,
  input  [1:0] a,
  output [1:0] c
);

  assign c = 2'h0;
endmodule


// ----- 8< ----- FILE "layers_Foo_A.sv" ----- 8< -----

// Generated by CIRCT firtool-1.81.1-18-g6aa871500
`ifndef layers_Foo_A
`define layers_Foo_A
`endif // layers_Foo_A