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[Scheduling] Explore support for SMT solvers
enhancement
New feature or request
Scheduling
#3624
opened Jul 28, 2022 by
mikeurbach
[Verif][Sim][Feature] Inline Simulation Tests
enhancement
New feature or request
Simulator
verif
#7479
opened Aug 8, 2024 by
dobios
[SCFToCalyx] Add support for The Calyx dialect
RegionBranchOpInterface
Calyx
#1871
opened Sep 23, 2021 by
mortbopet
[Verilator] Enable RTL simulation debugging
enhancement
New feature or request
#239
opened Nov 12, 2020 by
teqdruid
[ImportVerilog] Rename
Context
to Converter
ImportVerilog
#6745
opened Feb 25, 2024 by
fabianschuiki
Optimize dependence analysis in standard to handshake.
Handshake
#69
opened Aug 17, 2020 by
stephenneuendorffer
staticlogic needs a 'register' operation to pass control from one block to another.
StaticLogic
#122
opened Oct 5, 2020 by
stephenneuendorffer
[RTL] Need support for declarations of module parameters
enhancement
New feature or request
HW
Involving the `hw` dialect
[FIRRTL] Support for comments?
FIRRTL
Involving the `firrtl` dialect
#223
opened Nov 9, 2020 by
lattner
[ExportVerilog] Emit integer signedness in type
enhancement
New feature or request
HW
Involving the `hw` dialect
#397
opened Jan 5, 2021 by
teqdruid
[ExportVerilog] Should emit unsigned/signed for IntegerTypes which are not signless
#469
opened Jan 17, 2021 by
teqdruid
Handshake-runner should allow unbounded FIFOs
Handshake
#67
opened Aug 17, 2020 by
stephenneuendorffer
Lower bi-directional bundles to interfaces
enhancement
New feature or request
FIRRTL
Involving the `firrtl` dialect
#536
opened Jan 29, 2021 by
mikeurbach
[Handshake] New Handshake lowerings to target RTL/ESI/Comb/Seq dialects
enhancement
New feature or request
Handshake
#742
opened Mar 9, 2021 by
mikeurbach
CMake 3.20.0 triggers warnings concerning policies CMP0115 and CMP0116
#849
opened Mar 30, 2021 by
fabianschuiki
Add integration test cases for comparison const folding
FIRRTL
Involving the `firrtl` dialect
#852
opened Mar 30, 2021 by
fabianschuiki
Add flag for SV v.s. V emission
enhancement
New feature or request
Verilog/SystemVerilog
Involving a Verilog dialect
#512
opened Jan 26, 2021 by
darthscsi
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