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Issues list

[Verilator] Enable RTL simulation debugging enhancement New feature or request
#239 opened Nov 12, 2020 by teqdruid
[RTL] Need support for declarations of module parameters enhancement New feature or request HW Involving the `hw` dialect
#221 opened Nov 8, 2020 by lattner SiFive-3
[FIRRTL] Support for comments? FIRRTL Involving the `firrtl` dialect
#223 opened Nov 9, 2020 by lattner
[ExportVerilog] Emit integer signedness in type enhancement New feature or request HW Involving the `hw` dialect
#397 opened Jan 5, 2021 by teqdruid
Lower bi-directional bundles to interfaces enhancement New feature or request FIRRTL Involving the `firrtl` dialect
#536 opened Jan 29, 2021 by mikeurbach
[FIRRTL] FIRRTL to RTL Memory Lowering Needs to Handle All Read Under Write Behaviors bug Something isn't working FIRRTL Involving the `firrtl` dialect
#787 opened Mar 18, 2021 by seldridge SiFive-3
Support Verilog Implementation Limits enhancement New feature or request ExportVerilog
#808 opened Mar 23, 2021 by seldridge
4 tasks
SiFive-3
Add integration test cases for comparison const folding FIRRTL Involving the `firrtl` dialect
#852 opened Mar 30, 2021 by fabianschuiki
Add flag for SV v.s. V emission enhancement New feature or request Verilog/SystemVerilog Involving a Verilog dialect
#512 opened Jan 26, 2021 by darthscsi
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