Skip to content

[CIR][AMDGPU] Adds lowering for amdgcn raw buffer load/store and atomics #2075

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
ranapratap55 wants to merge 1 commit into
base: main
Choose a base branch
from
Open

[CIR][AMDGPU] Adds lowering for amdgcn raw buffer load/store and atomics #2075

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
67 changes: 53 additions & 14 deletions clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -769,31 +769,70 @@ mlir::Value CIRGenFunction::emitAMDGPUBuiltinExpr(unsigned builtinId,
case AMDGPU::BI__builtin_amdgcn_raw_buffer_store_b64:
case AMDGPU::BI__builtin_amdgcn_raw_buffer_store_b96:
case AMDGPU::BI__builtin_amdgcn_raw_buffer_store_b128: {
llvm_unreachable("raw_buffer_store_* NYI");
mlir::Type voidTy = cir::VoidType::get(builder.getContext());
llvm::SmallVector<mlir::Value, 5> Args;
for (unsigned I = 0; I < 5; ++I)
Args.push_back(emitScalarExpr(expr->getArg(I)));
auto CallOp = LLVMIntrinsicCallOp::create(
builder, getLoc(expr->getExprLoc()),
builder.getStringAttr("amdgcn.raw.ptr.buffer.store"), voidTy, Args);
return CallOp.getResult();
}
case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b8:
case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b16:
case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b32:
case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b64:
case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b96:
case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b128: {
llvm_unreachable("raw_buffer_load_* NYI");
}
case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_add_i32: {
llvm_unreachable("raw_ptr_buffer_atomic_add_* NYI");
mlir::Type retTy;
switch (builtinId) {
case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b8:
retTy = builder.getUIntNTy(8);
break;
case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b16:
retTy = builder.getUIntNTy(16);
break;
case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b32:
retTy = builder.getUIntNTy(32);
break;
case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b64:
retTy = cir::VectorType::get(builder.getUIntNTy(32), 2);
break;
case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b96:
retTy = cir::VectorType::get(builder.getUIntNTy(32), 3);
break;
case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b128:
retTy = cir::VectorType::get(builder.getUIntNTy(32), 4);
break;
}
return LLVMIntrinsicCallOp::create(
builder, getLoc(expr->getExprLoc()),
builder.getStringAttr("amdgcn.raw.ptr.buffer.load"), retTy,
{emitScalarExpr(expr->getArg(0)),
emitScalarExpr(expr->getArg(1)),
emitScalarExpr(expr->getArg(2)),
emitScalarExpr(expr->getArg(3))})
.getResult();
}
case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_add_i32:
return emitBuiltinWithOneOverloadedType<5>(
expr, "amdgcn.raw.ptr.buffer.atomic.add")
.getScalarVal();
case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fadd_f32:
case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fadd_v2f16: {
llvm_unreachable("raw_ptr_buffer_atomic_fadd_* NYI");
}
case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fadd_v2f16:
return emitBuiltinWithOneOverloadedType<5>(
expr, "amdgcn.raw.ptr.buffer.atomic.fadd")
.getScalarVal();
case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fmin_f32:
case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fmin_f64: {
llvm_unreachable("raw_ptr_buffer_atomic_fmin_* NYI");
}
case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fmin_f64:
return emitBuiltinWithOneOverloadedType<5>(
expr, "amdgcn.raw.ptr.buffer.atomic.fmin")
.getScalarVal();
case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fmax_f32:
case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fmax_f64: {
llvm_unreachable("raw_ptr_buffer_atomic_fmax_* NYI");
}
case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fmax_f64:
return emitBuiltinWithOneOverloadedType<5>(
expr, "amdgcn.raw.ptr.buffer.atomic.fmax")
.getScalarVal();
case AMDGPU::BI__builtin_amdgcn_s_prefetch_data: {
llvm_unreachable("s_prefetch_data_* NYI");
}
Expand Down
8 changes: 7 additions & 1 deletion clang/lib/CIR/CodeGen/CIRGenTypes.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -589,7 +589,13 @@ mlir::Type CIRGenTypes::convertType(QualType T) {
#include "clang/Basic/WebAssemblyReferenceTypes.def"
#define AMDGPU_OPAQUE_PTR_TYPE(Name, Id, SingletonId, Width, Align, AS) \
case BuiltinType::Id: \
ResultType = Builder.getPointerTo(CGM.VoidTy); \
if (AS == 0) { \
ResultType = Builder.getPointerTo(CGM.VoidTy); \
} else { \
ResultType = Builder.getPointerTo( \
CGM.VoidTy, \
cir::TargetAddressSpaceAttr::get(&getMLIRContext(), AS)); \
} \
break;
#define AMDGPU_NAMED_BARRIER_TYPE(Name, Id, SingletonId, Width, Align, Scope) \
case BuiltinType::Id: \
Expand Down
93 changes: 93 additions & 0 deletions clang/test/CIR/CodeGen/HIP/builtins-amdgcn-raw-buffer-atomics.hip
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,93 @@
#include "../Inputs/cuda.h"

// REQUIRES: amdgpu-registered-target
// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -std=c++11 -fclangir \
// RUN: -target-cpu gfx90a -fcuda-is-device -emit-cir %s -o %t.cir
// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s

// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -std=c++11 -fclangir \
// RUN: -target-cpu gfx90a -fcuda-is-device -emit-llvm %s -o %t.ll
// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s

// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -std=c++11 \
// RUN: -target-cpu gfx90a -fcuda-is-device \
// RUN: -target-feature +atomic-fmin-fmax-global-f32 \
// RUN: -target-feature +atomic-fmin-fmax-global-f64 \
// RUN: -emit-llvm %s -o %t.ll
// RUN: FileCheck --check-prefix=OGCG --input-file=%t.ll %s

//===----------------------------------------------------------------------===//
// Test raw buffer atomic builtins
//===----------------------------------------------------------------------===//

typedef _Float16 __attribute__((ext_vector_type(2))) float16x2_t;

// CIR-LABEL: @_Z19test_atomic_add_i32
// CIR: cir.llvm.intrinsic "amdgcn.raw.ptr.buffer.atomic.add" {{.*}} : (!s32i, !cir.ptr<!void, target_address_space(8)>, !s32i, !s32i, !s32i) -> !s32i
// LLVM-LABEL: define{{.*}} i32 @_Z19test_atomic_add_i32
// LLVM: call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add.i32(i32 %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
// OGCG-LABEL: define{{.*}} i32 @_Z19test_atomic_add_i32
// OGCG: call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add.i32(i32 %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
__device__ int test_atomic_add_i32(int x, __amdgpu_buffer_rsrc_t rsrc, int offset, int soffset) {
return __builtin_amdgcn_raw_ptr_buffer_atomic_add_i32(x, rsrc, offset, soffset, 0);
}

// CIR-LABEL: @_Z20test_atomic_fadd_f32
// CIR: cir.llvm.intrinsic "amdgcn.raw.ptr.buffer.atomic.fadd" {{.*}} : (!cir.float, !cir.ptr<!void, target_address_space(8)>, !s32i, !s32i, !s32i) -> !cir.float
// LLVM-LABEL: define{{.*}} float @_Z20test_atomic_fadd_f32
// LLVM: call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
// OGCG-LABEL: define{{.*}} float @_Z20test_atomic_fadd_f32
// OGCG: call {{.*}}float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
__device__ float test_atomic_fadd_f32(float x, __amdgpu_buffer_rsrc_t rsrc, int offset, int soffset) {
return __builtin_amdgcn_raw_ptr_buffer_atomic_fadd_f32(x, rsrc, offset, soffset, 0);
}

// CIR-LABEL: @_Z22test_atomic_fadd_v2f16
// CIR: cir.llvm.intrinsic "amdgcn.raw.ptr.buffer.atomic.fadd" {{.*}} : (!cir.vector<!cir.f16 x 2>, !cir.ptr<!void, target_address_space(8)>, !s32i, !s32i, !s32i) -> !cir.vector<!cir.f16 x 2>
// LLVM-LABEL: define{{.*}} <2 x half> @_Z22test_atomic_fadd_v2f16
// LLVM: call <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half> %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
// OGCG-LABEL: define{{.*}} <2 x half> @_Z22test_atomic_fadd_v2f16
// OGCG: call {{.*}}<2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half> %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
__device__ float16x2_t test_atomic_fadd_v2f16(float16x2_t x, __amdgpu_buffer_rsrc_t rsrc, int offset, int soffset) {
return __builtin_amdgcn_raw_ptr_buffer_atomic_fadd_v2f16(x, rsrc, offset, soffset, 0);
}

// CIR-LABEL: @_Z20test_atomic_fmin_f32
// CIR: cir.llvm.intrinsic "amdgcn.raw.ptr.buffer.atomic.fmin" {{.*}} : (!cir.float, !cir.ptr<!void, target_address_space(8)>, !s32i, !s32i, !s32i) -> !cir.float
// LLVM-LABEL: define{{.*}} float @_Z20test_atomic_fmin_f32
// LLVM: call float @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f32(float %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
// OGCG-LABEL: define{{.*}} float @_Z20test_atomic_fmin_f32
// OGCG: call {{.*}}float @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f32(float %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
__device__ float test_atomic_fmin_f32(float x, __amdgpu_buffer_rsrc_t rsrc, int offset, int soffset) {
return __builtin_amdgcn_raw_ptr_buffer_atomic_fmin_f32(x, rsrc, offset, soffset, 0);
}

// CIR-LABEL: @_Z20test_atomic_fmin_f64
// CIR: cir.llvm.intrinsic "amdgcn.raw.ptr.buffer.atomic.fmin" {{.*}} : (!cir.double, !cir.ptr<!void, target_address_space(8)>, !s32i, !s32i, !s32i) -> !cir.double
// LLVM-LABEL: define{{.*}} double @_Z20test_atomic_fmin_f64
// LLVM: call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
// OGCG-LABEL: define{{.*}} double @_Z20test_atomic_fmin_f64
// OGCG: call {{.*}}double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
__device__ double test_atomic_fmin_f64(double x, __amdgpu_buffer_rsrc_t rsrc, int offset, int soffset) {
return __builtin_amdgcn_raw_ptr_buffer_atomic_fmin_f64(x, rsrc, offset, soffset, 0);
}

// CIR-LABEL: @_Z20test_atomic_fmax_f32
// CIR: cir.llvm.intrinsic "amdgcn.raw.ptr.buffer.atomic.fmax" {{.*}} : (!cir.float, !cir.ptr<!void, target_address_space(8)>, !s32i, !s32i, !s32i) -> !cir.float
// LLVM-LABEL: define{{.*}} float @_Z20test_atomic_fmax_f32
// LLVM: call float @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f32(float %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
// OGCG-LABEL: define{{.*}} float @_Z20test_atomic_fmax_f32
// OGCG: call {{.*}}float @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f32(float %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
__device__ float test_atomic_fmax_f32(float x, __amdgpu_buffer_rsrc_t rsrc, int offset, int soffset) {
return __builtin_amdgcn_raw_ptr_buffer_atomic_fmax_f32(x, rsrc, offset, soffset, 0);
}

// CIR-LABEL: @_Z20test_atomic_fmax_f64
// CIR: cir.llvm.intrinsic "amdgcn.raw.ptr.buffer.atomic.fmax" {{.*}} : (!cir.double, !cir.ptr<!void, target_address_space(8)>, !s32i, !s32i, !s32i) -> !cir.double
// LLVM-LABEL: define{{.*}} double @_Z20test_atomic_fmax_f64
// LLVM: call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
// OGCG-LABEL: define{{.*}} double @_Z20test_atomic_fmax_f64
// OGCG: call {{.*}}double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %{{.*}}, ptr addrspace(8) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 0)
__device__ double test_atomic_fmax_f64(double x, __amdgpu_buffer_rsrc_t rsrc, int offset, int soffset) {
return __builtin_amdgcn_raw_ptr_buffer_atomic_fmax_f64(x, rsrc, offset, soffset, 0);
}
Loading