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[AArch64] Disable machine-verifier for failing test, fix perf regression #140005

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Merged
merged 2 commits into from
May 15, 2025
Merged

[AArch64] Disable machine-verifier for failing test, fix perf regression #140005

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533a31e
[AArch64] Disable machine-verifier for failing test, fix perf regression
yasuna-oribe May 15, 2025
75eaac1
amend! [AArch64] Disable machine-verifier for failing test, fix perf …
yasuna-oribe May 15, 2025
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12 changes: 7 additions & 5 deletions llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3611,6 +3611,9 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
unsigned ExtraCSSpill = 0;
bool HasUnpairedGPR64 = false;
bool HasPairZReg = false;
BitVector UserReservedRegs = RegInfo->getUserReservedRegs(MF);
BitVector ReservedRegs = RegInfo->getReservedRegs(MF);

// Figure out which callee-saved registers to save/restore.
for (unsigned i = 0; CSRegs[i]; ++i) {
const unsigned Reg = CSRegs[i];
Expand All @@ -3621,7 +3624,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,

// Don't save manually reserved registers set through +reserve-x#i,
// even for callee-saved registers, as per GCC's behavior.
if (RegInfo->isUserReservedReg(MF, Reg)) {
if (UserReservedRegs[Reg]) {
SavedRegs.reset(Reg);
continue;
}
Expand Down Expand Up @@ -3653,8 +3656,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
AArch64::FPR128RegClass.contains(Reg, PairedReg));

if (!RegUsed) {
if (AArch64::GPR64RegClass.contains(Reg) &&
!RegInfo->isReservedReg(MF, Reg)) {
if (AArch64::GPR64RegClass.contains(Reg) && !ReservedRegs[Reg]) {
UnspilledCSGPR = Reg;
UnspilledCSGPRPaired = PairedReg;
}
Expand All @@ -3676,7 +3678,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
!SavedRegs.test(PairedReg)) {
SavedRegs.set(PairedReg);
if (AArch64::GPR64RegClass.contains(PairedReg) &&
!RegInfo->isReservedReg(MF, PairedReg))
!ReservedRegs[PairedReg])
ExtraCSSpill = PairedReg;
}
// Check if there is a pair of ZRegs, so it can select PReg for spill/fill
Expand All @@ -3699,7 +3701,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
AFI->setPredicateRegForFillSpill(AArch64::PN8);
}

assert(!RegInfo->isReservedReg(MF, AFI->getPredicateRegForFillSpill()) &&
assert(!ReservedRegs[AFI->getPredicateRegForFillSpill()] &&
"Predicate cannot be a reserved register");
}

Expand Down
3 changes: 2 additions & 1 deletion llvm/test/CodeGen/AArch64/reserveXreg.ll
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Original file line number Diff line number Diff line change
@@ -1,8 +1,9 @@
;; Check if manually reserved registers are always excluded from being saved by
;; the function prolog/epilog, even for callee-saved ones, as per GCC behavior.
;; Look at AArch64Features.td for registers excluded from this test.
;; FIXME: Fix machine verifier issues and remove -verify-machineinstrs=0.

; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -verify-machineinstrs=0 | FileCheck %s

define preserve_mostcc void @t1() "target-features"="+reserve-x1" {
; CHECK-LABEL: t1:
Expand Down