[SPIR-V] Add support for the SPIR-V extension SPV_INTEL_tensor_float32_conversion #150090

YixingZhang007 · 2025-07-22T19:18:04Z

This PR introduces the support for the SPIR-V extension SPV_INTEL_tensor_float32_conversion and the corresponding OpenCL extension cl_intel_tensor_float32_conversions.
This extension introduces a rounding instruction that converts standard 32-bit floating-point values to the TensorFloat32 (TF32) format.

Reference Specification:
https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_tensor_float32_conversion.asciidoc

github-actions · 2025-07-22T19:18:25Z

Thank you for submitting a Pull Request (PR) to the LLVM Project!

This PR will be automatically labeled and the relevant teams will be notified.

If you wish to, you can add reviewers by using the "Reviewers" section on this page.

If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using @ followed by their GitHub username.

If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers.

If you have further questions, they may be answered by the LLVM GitHub User Guide.

You can also ask questions in a comment on this PR, on the LLVM Discord or on the forums.

llvmbot · 2025-07-22T19:19:04Z

@llvm/pr-subscribers-mlir
@llvm/pr-subscribers-mlir-spirv

@llvm/pr-subscribers-backend-spir-v

Author: None (YixingZhang007)

Changes

This PR is to add support for the SPIR-V extension SPV_INTEL_tensor_float32_conversion (https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_tensor_float32_conversion.asciidoc)

Full diff: https://github.com/llvm/llvm-project/pull/150090.diff

5 Files Affected:

(modified) llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp (+15-2)
(modified) llvm/lib/Target/SPIRV/SPIRVBuiltins.td (+20-1)
(modified) llvm/lib/Target/SPIRV/SPIRVInstrInfo.td (+4-1)
(modified) llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp (+6)
(modified) llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td (+2)

diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 6ec7544767c52..1c7c1750af1c9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -148,6 +148,7 @@ struct ConvertBuiltin {
   bool IsSaturated;
   bool IsRounded;
   bool IsBfloat16;
+  bool IsTF32;
   FPRoundingMode::FPRoundingMode RoundingMode;
 };
 
@@ -2677,8 +2678,20 @@ static bool generateConvertInst(const StringRef DemangledCall,
       }
     } else if (GR->isScalarOrVectorOfType(Call->ReturnRegister,
                                           SPIRV::OpTypeFloat)) {
-      // Float -> Float
-      Opcode = SPIRV::OpFConvert;
+      if(Builtin->IsTF32){
+        const auto *ST = static_cast<const SPIRVSubtarget *>(
+          &MIRBuilder.getMF().getSubtarget());
+        if (!ST->canUseExtension(
+                SPIRV::Extension::SPV_INTEL_bfloat16_conversion))
+          NeedExtMsg = "SPV_INTEL_bfloat16_conversion";
+          IsRightComponentsNumber =
+            GR->getScalarOrVectorComponentCount(Call->Arguments[0]) ==
+            GR->getScalarOrVectorComponentCount(Call->ReturnRegister);
+        Opcode = SPIRV::OpRoundFToTF32INTEL;
+      } else {
+        Float -> Float
+        Opcode = SPIRV::OpFConvert;
+      }
     }
   }
 
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index ea78dcd135267..326109c9fdff4 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -1461,6 +1461,7 @@ class ConvertBuiltin<string name, InstructionSet set> {
   bit IsRounded = !not(!eq(!find(name, "_rt"), -1));
   bit IsBfloat16 = !or(!not(!eq(!find(name, "BF16"), -1)),
                        !not(!eq(!find(name, "bfloat16"), -1)));
+  bit IsTF32 = !not(!eq(!find(name, "TF32"), -1));
   FPRoundingMode RoundingMode = !cond(!not(!eq(!find(name, "_rte"), -1)) : RTE,
                                   !not(!eq(!find(name, "_rtz"), -1)) : RTZ,
                                   !not(!eq(!find(name, "_rtp"), -1)) : RTP,
@@ -1472,7 +1473,7 @@ class ConvertBuiltin<string name, InstructionSet set> {
 def ConvertBuiltins : GenericTable {
   let FilterClass = "ConvertBuiltin";
   let Fields = ["Name", "Set", "IsDestinationSigned", "IsSaturated",
-                "IsRounded", "IsBfloat16", "RoundingMode"];
+                "IsRounded", "IsBfloat16", "IsTF32", "RoundingMode"];
   string TypeOf_Set = "InstructionSet";
   string TypeOf_RoundingMode = "FPRoundingMode";
 }
@@ -1556,6 +1557,24 @@ foreach conv = ["FToBF16INTEL", "BF16ToFINTEL"] in {
   def : ConvertBuiltin<!strconcat("__spirv_Convert", conv), OpenCL_std>;
 }
 
+// SPV_INTEL_tensor_float32_conversion
+// Multiclass used to define at the same time both a demangled builtin records
+// and a corresponding convert builtin records.
+multiclass DemangledTF32ConvertBuiltin<string name1, string name2> {
+  // Create records for scalar and vector conversions.
+  foreach i = ["", "2", "3", "4", "8", "16"] in {
+    def : DemangledBuiltin<!strconcat("intel_convert_", name1, i, name2, i), OpenCL_std, Convert, 1, 1>;
+    def : ConvertBuiltin<!strconcat("intel_convert_", name1, i, name2, i), OpenCL_std>;
+  }
+}
+
+defm : DemangledTF32ConvertBuiltin<"ConvertFToTF32INTEL">;
+
+foreach conv = ["FToTF32INTEL"] in {
+  def : DemangledBuiltin<!strconcat("__spirv_Convert", conv), OpenCL_std, Convert, 1, 1>;
+  def : ConvertBuiltin<!strconcat("__spirv_Convert", conv), OpenCL_std>;
+}
+
 //===----------------------------------------------------------------------===//
 // Class defining a vector data load/store builtin record used for lowering
 // into OpExtInst instruction.
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 049ba0275f223..a04ed6a42c868 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -441,10 +441,13 @@ def OpBitcast : UnOp<"OpBitcast", 124>;
 def OpPtrCastToCrossWorkgroupINTEL : UnOp<"OpPtrCastToCrossWorkgroupINTEL", 5934>;
 def OpCrossWorkgroupCastToPtrINTEL : UnOp<"OpCrossWorkgroupCastToPtrINTEL", 5938>;
 
-// SPV_INTEL_bfloat16_conversion
+// SPV_INTEL_tensor_float32_conversion
 def OpConvertFToBF16INTEL : UnOp<"OpConvertFToBF16INTEL", 6116>;
 def OpConvertBF16ToFINTEL : UnOp<"OpConvertBF16ToFINTEL", 6117>;
 
+// SPV_INTEL_bfloat16_conversion
+def OpRoundFToTF32INTEL : UnOp<"OpRoundFToTF32INTEL", 6426>;
+
 // 3.42.12 Composite Instructions
 
 def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index ad976e5288927..c252fc5897518 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1564,6 +1564,12 @@ void addInstrRequirements(const MachineInstr &MI,
       Reqs.addCapability(SPIRV::Capability::BFloat16ConversionINTEL);
     }
     break;
+  case SPIRV::OpRoundFToTF32INTEL:
+    if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_tensor_float32_conversion)) {
+      Reqs.addExtension(SPIRV::Extension::SPV_INTEL_tensor_float32_conversion);
+      Reqs.addCapability(SPIRV::Capability::TF32ConversionINTEL);
+    }
+    break;
   case SPIRV::OpVariableLengthArrayINTEL:
   case SPIRV::OpSaveMemoryINTEL:
   case SPIRV::OpRestoreMemoryINTEL:
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index 548e9b717c161..7b2139a1c84a8 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -320,6 +320,7 @@ defm SPV_INTEL_subgroup_matrix_multiply_accumulate : ExtensionOperand<121>;
 defm SPV_INTEL_2d_block_io : ExtensionOperand<122>;
 defm SPV_INTEL_int4 : ExtensionOperand<123>;
 defm SPV_KHR_float_controls2 : ExtensionOperand<124>;
+defm SPV_INTEL_tensor_float32_conversion : ExtensionOperand<125>;
 
 //===----------------------------------------------------------------------===//
 // Multiclass used to define Capabilities enum values and at the same time
@@ -502,6 +503,7 @@ defm VariableLengthArrayINTEL : CapabilityOperand<5817, 0, 0, [SPV_INTEL_variabl
 defm GroupUniformArithmeticKHR : CapabilityOperand<6400, 0, 0, [SPV_KHR_uniform_group_instructions], []>;
 defm USMStorageClassesINTEL : CapabilityOperand<5935, 0, 0, [SPV_INTEL_usm_storage_classes], [Kernel]>;
 defm BFloat16ConversionINTEL : CapabilityOperand<6115, 0, 0, [SPV_INTEL_bfloat16_conversion], []>;
+defm TF32ConversionINTEL : CapabilityOperand<6425, 0, 0, [SPV_INTEL_tensor_float32_conversion], []>;
 defm GlobalVariableHostAccessINTEL : CapabilityOperand<6187, 0, 0, [SPV_INTEL_global_variable_host_access], []>;
 defm HostAccessINTEL : CapabilityOperand<6188, 0, 0, [SPV_INTEL_global_variable_host_access], []>;
 defm GlobalVariableFPGADecorationsINTEL : CapabilityOperand<6189, 0, 0, [SPV_INTEL_global_variable_fpga_decorations], []>;

github-actions · 2025-07-23T14:46:21Z

✅ With the latest revision this PR passed the C/C++ code formatter.

Hardcode84 · 2025-07-30T08:43:17Z

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVIntelExtOps.td

+
+
+    ```
+    convert-f-to-tf32-op ::= ssa-id `=` `spirv.INTEL.RoundFToTF32` ssa-use


I think, grammar is being generated from the op definition itself, so you don't need to specify it manually.

Thanks for the suggestion! I have made the modification (The MLIR part of this PR have been moved to a new PR #151337 and changes are made there)

Hardcode84 · 2025-07-30T08:50:33Z

mlir/lib/Dialect/SPIRV/IR/CastOps.cpp

+  if (auto vectorType = llvm::dyn_cast<VectorType>(operandType)) {
+    unsigned operandNumElements = vectorType.getNumElements();
+    unsigned resultNumElements =
+        llvm::cast<VectorType>(resultType).getNumElements();


Please check if resultType is actually a vector. Also, I think we need to check if both vectors are non-scalable.

Also, you can drop llvm:: before the casts as they are reimported into mlir namespace

Thanks for the suggestion! I have added the vector non-scalable check and update the code as following:

auto operandVectorType = dyn_cast<VectorType>(operandType); auto resultVectorType = dyn_cast<VectorType>(resultType); if (operandVectorType && resultVectorType) { if (operandVectorType.isScalable() || resultVectorType.isScalable()) { return emitOpError("scalable vectors are not supported"); } if (operandVectorType.getNumElements() != resultVectorType.getNumElements()) { return emitOpError( "operand and result must have same number of elements"); } }

Similar changes are also made for INTELConvertFToBF16Op and INTELConvertBF16ToFOp as they are having the same problems. The MLIR part of this PR have been moved to a new PR #151337 and these changes are made there. :)

MrSidims

SPIR-V backend part of the PR is LGTM.

kuhar

Can we land mlir support separately from the llvm backend? This should make it easier to review and potentially revert in the future.

YixingZhang007 · 2025-07-30T13:57:49Z

Can we land mlir support separately from the llvm backend? This should make it easier to review and potentially revert in the future.

Thanks for the suggestion :) I have moved the mlir part to a new PR. The link to mlir PR is #151337.

maarquitos14 · 2025-07-30T15:03:16Z

llvm/lib/Target/SPIRV/SPIRVBuiltins.td

+// Multiclass used to define at the same time both a demangled builtin records
+// and a corresponding convert builtin records.


Suggested change

// Multiclass used to define at the same time both a demangled builtin records

// and a corresponding convert builtin records.

// Multiclass used to define at the same time both a demangled builtin record

// and a corresponding convert builtin record.

I think?

Thanks! I have fixed this :)

maarquitos14

LGTM.

YixingZhang007 marked this pull request as draft July 22, 2025 19:18

llvmbot added the backend:SPIR-V label Jul 22, 2025

YixingZhang007 force-pushed the add_SPV_INTEL_tensor_float32_conversion branch from 0ded7d2 to b439ab2 Compare July 29, 2025 22:01

YixingZhang007 marked this pull request as ready for review July 29, 2025 22:01

YixingZhang007 requested review from antiagainst and kuhar as code owners July 29, 2025 22:01

llvmbot added mlir:spirv mlir labels Jul 29, 2025

kuhar requested review from krzysz00 and Hardcode84 July 30, 2025 01:15

YixingZhang007 added 4 commits July 29, 2025 19:43

draft implementation for supporting SPV_INTEL_tensor_float32_conversion

3749aa6

add tests, finalize the implementation and code cleanup

b90fd0c

fix clang format

6135f14

fix the CI test failure

8528c2f

YixingZhang007 force-pushed the add_SPV_INTEL_tensor_float32_conversion branch from b439ab2 to 8528c2f Compare July 30, 2025 03:07

Hardcode84 reviewed Jul 30, 2025

View reviewed changes

MrSidims requested review from Naghasan and MrSidims July 30, 2025 11:21

MrSidims approved these changes Jul 30, 2025

View reviewed changes

kuhar reviewed Jul 30, 2025

View reviewed changes

move the mlir part to a new PR

5b4b793

maarquitos14 reviewed Jul 30, 2025

View reviewed changes

solve the grammar mistake

608c8fa

MrSidims requested a review from maarquitos14 July 31, 2025 12:18

maarquitos14 reviewed Jul 31, 2025

View reviewed changes

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

[SPIR-V] Add support for the SPIR-V extension SPV_INTEL_tensor_float32_conversion #150090

[SPIR-V] Add support for the SPIR-V extension SPV_INTEL_tensor_float32_conversion #150090

Uh oh!

YixingZhang007 commented Jul 22, 2025 •

edited

Loading

Uh oh!

github-actions bot commented Jul 22, 2025

Uh oh!

llvmbot commented Jul 22, 2025 •

edited

Loading

Uh oh!

github-actions bot commented Jul 23, 2025 •

edited

Loading

Uh oh!

Hardcode84 Jul 30, 2025

Uh oh!

YixingZhang007 Jul 30, 2025

Uh oh!

Hardcode84 Jul 30, 2025

Uh oh!

Hardcode84 Jul 30, 2025

Uh oh!

YixingZhang007 Jul 30, 2025 •

edited

Loading

Uh oh!

MrSidims left a comment

Uh oh!

kuhar left a comment

Uh oh!

YixingZhang007 commented Jul 30, 2025

Uh oh!

maarquitos14 Jul 30, 2025

Uh oh!

YixingZhang007 Jul 30, 2025

Uh oh!

maarquitos14 left a comment

Uh oh!

Uh oh!



		```
		convert-f-to-tf32-op ::= ssa-id `=` `spirv.INTEL.RoundFToTF32` ssa-use

		// Multiclass used to define at the same time both a demangled builtin records
		// and a corresponding convert builtin records.

[SPIR-V] Add support for the SPIR-V extension SPV_INTEL_tensor_float32_conversion #150090

Are you sure you want to change the base?

[SPIR-V] Add support for the SPIR-V extension SPV_INTEL_tensor_float32_conversion #150090

Uh oh!

Conversation

YixingZhang007 commented Jul 22, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

github-actions bot commented Jul 22, 2025

Uh oh!

llvmbot commented Jul 22, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

github-actions bot commented Jul 23, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

Hardcode84 Jul 30, 2025

Choose a reason for hiding this comment

Uh oh!

YixingZhang007 Jul 30, 2025

Choose a reason for hiding this comment

Uh oh!

Hardcode84 Jul 30, 2025

Choose a reason for hiding this comment

Uh oh!

Hardcode84 Jul 30, 2025

Choose a reason for hiding this comment

Uh oh!

YixingZhang007 Jul 30, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

MrSidims left a comment

Choose a reason for hiding this comment

Uh oh!

kuhar left a comment

Choose a reason for hiding this comment

Uh oh!

YixingZhang007 commented Jul 30, 2025

Uh oh!

maarquitos14 Jul 30, 2025

Choose a reason for hiding this comment

Uh oh!

YixingZhang007 Jul 30, 2025

Choose a reason for hiding this comment

Uh oh!

maarquitos14 left a comment

Choose a reason for hiding this comment

Uh oh!

Uh oh!

YixingZhang007 commented Jul 22, 2025 •

edited

Loading

llvmbot commented Jul 22, 2025 •

edited

Loading

github-actions bot commented Jul 23, 2025 •

edited

Loading

YixingZhang007 Jul 30, 2025 •

edited

Loading