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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -19076,7 +19076,7 @@ static SDValue performUADDVCombine(SDNode *N, SelectionDAG &DAG) {
}

// uaddv(A) --> A if all lanes of A are known to be zeros except the 0th lane.
MVT VT = N->getSimpleValueType(0);
[[maybe_unused]] MVT VT = N->getSimpleValueType(0);
MVT OpVT = A.getSimpleValueType();
assert(VT == OpVT &&
"The operand type should be consistent with the result type of UADDV");
Expand Down