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Merged
rivos-eblot merged 3 commits into from
Dec 5, 2025
Merged

opentitan: update HWADDR printf-like formatters. #307

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e6792b3
[ot] hw/opentitan: ot_darjeeling: remove orphan reference file.
rivos-eblot Dec 5, 2025
d6f8903
[ot] hw/opentitan: opentitan: do not use HWADDR_PRIx to format 32-bit…
rivos-eblot Dec 4, 2025
633c638
[ot] hw/opentitan: opentitan: update formatter width specifier for 32…
rivos-eblot Dec 4, 2025
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2 changes: 1 addition & 1 deletion docs/opentitan/ot_darjeeling.md
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

## Supported version

Please check out `hw/opentitan/ot_ref.log`
Please check out the `ot_darjeeling.c` file header.

## Supported devices

Expand Down
20 changes: 8 additions & 12 deletions hw/opentitan/ot_aes.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1132,9 +1132,8 @@ static uint64_t ot_aes_read(void *opaque, hwaddr addr, unsigned size)
case R_DATA_IN_2:
case R_DATA_IN_3:
case R_TRIGGER:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
__func__, s->ot_id, addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
__func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
val32 = 0u;
break;
case R_IV_0:
Expand Down Expand Up @@ -1174,9 +1173,8 @@ static uint64_t ot_aes_read(void *opaque, hwaddr addr, unsigned size)
}
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
s->ot_id, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
s->ot_id, (uint32_t)addr);
val32 = 0u;
break;
}
Expand Down Expand Up @@ -1216,9 +1214,8 @@ static void ot_aes_write(void *opaque, hwaddr addr, uint64_t val64,
case R_DATA_OUT_2:
case R_DATA_OUT_3:
case R_STATUS:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
__func__, s->ot_id, addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
__func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
break;
case R_KEY_SHARE0_0:
case R_KEY_SHARE0_1:
Expand Down Expand Up @@ -1336,9 +1333,8 @@ static void ot_aes_write(void *opaque, hwaddr addr, uint64_t val64,
ot_aes_handle_trigger(s);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
s->ot_id, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
s->ot_id, (uint32_t)addr);
break;
}
};
Expand Down
10 changes: 4 additions & 6 deletions hw/opentitan/ot_alert.c
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Original file line number Diff line number Diff line change
Expand Up @@ -814,9 +814,8 @@ static uint64_t ot_alert_regs_read(void *opaque, hwaddr addr, unsigned size)
hwaddr reg = R32_OFF(addr);

if (reg >= s->reg_count) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s:Invalid register 0x%03" HWADDR_PRIx "\n", __func__,
addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid register 0x%03x\n",
__func__, (uint32_t)addr);
return 0;
}

Expand All @@ -843,9 +842,8 @@ static void ot_alert_regs_write(void *opaque, hwaddr addr, uint64_t val64,
pc);

if (reg >= s->reg_count) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s:Invalid register 0x%03" HWADDR_PRIx "\n", __func__,
addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid register 0x%03x\n",
__func__, (uint32_t)addr);
return;
}

Expand Down
13 changes: 6 additions & 7 deletions hw/opentitan/ot_aon_timer.c
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Original file line number Diff line number Diff line change
Expand Up @@ -401,14 +401,13 @@ static uint64_t ot_aon_timer_read(void *opaque, hwaddr addr, unsigned size)
}
case R_ALERT_TEST:
case R_INTR_TEST:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
__func__, (uint32_t)addr, REG_NAME(reg));
val32 = 0;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
(uint32_t)addr);
val32 = 0;
break;
}
Expand Down Expand Up @@ -548,8 +547,8 @@ static void ot_aon_timer_write(void *opaque, hwaddr addr, uint64_t value,
/* ignore write, in QEMU wkup_cause is always 0 */
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
(uint32_t)addr);
}
}

Expand Down
8 changes: 4 additions & 4 deletions hw/opentitan/ot_ast_dj.c
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Original file line number Diff line number Diff line change
Expand Up @@ -389,8 +389,8 @@ static uint64_t ot_ast_dj_regs_read(void *opaque, hwaddr addr, unsigned size)
val32 = s->regsb[reg - R_REGB0];
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
(uint32_t)addr);
val32 = 0;
break;
}
Expand Down Expand Up @@ -463,8 +463,8 @@ static void ot_ast_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
s->regsb[reg - R_REGB0] = val32;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
(uint32_t)addr);
break;
}
};
Expand Down
8 changes: 4 additions & 4 deletions hw/opentitan/ot_ast_eg.c
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Original file line number Diff line number Diff line change
Expand Up @@ -387,8 +387,8 @@ static uint64_t ot_ast_eg_regs_read(void *opaque, hwaddr addr, unsigned size)
val32 = s->regsb[reg - R_REGB0];
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
(uint32_t)addr);
val32 = 0;
break;
}
Expand Down Expand Up @@ -461,8 +461,8 @@ static void ot_ast_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
s->regsb[reg - R_REGB0] = val32;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
(uint32_t)addr);
break;
}
};
Expand Down
23 changes: 10 additions & 13 deletions hw/opentitan/ot_clkmgr.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1032,9 +1032,8 @@ static uint64_t ot_clkmgr_read(void *opaque, hwaddr addr, unsigned size)
val32 = ot_clkmgr_get_clock_hints(s);
break;
case R_ALERT_TEST:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
__func__, (uint32_t)addr, REG_NAME(reg));
val32 = 0;
break;
default:
Expand Down Expand Up @@ -1096,8 +1095,8 @@ static uint64_t ot_clkmgr_read(void *opaque, hwaddr addr, unsigned size)
break;
default:
val32 = 0;
qemu_log_mask(LOG_GUEST_ERROR, "%s: bad offset 0x%" HWADDR_PRIx "\n",
__func__, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: bad offset 0x%02x\n", __func__,
(uint32_t)addr);
break;
}

Expand Down Expand Up @@ -1181,9 +1180,8 @@ static void ot_clkmgr_write(void *opaque, hwaddr addr, uint64_t val64,
break;
case R_EXTCLK_STATUS:
case R_CLK_HINTS_STATUS:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
__func__, (uint32_t)addr, REG_NAME(reg));
break;
default:
break;
Expand Down Expand Up @@ -1271,13 +1269,12 @@ static void ot_clkmgr_write(void *opaque, hwaddr addr, uint64_t val64,
s->regs[reg_err] &= ~val32; /* RW1C */
break;
case R_FATAL_ERR_CODE:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
__func__, (uint32_t)addr, REG_NAME(reg));
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: bad offset 0x%" HWADDR_PRIx "\n",
__func__, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: bad offset 0x%02x\n", __func__,
(uint32_t)addr);
break;
}
};
Expand Down
18 changes: 8 additions & 10 deletions hw/opentitan/ot_csrng.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1750,14 +1750,13 @@ static uint64_t ot_csrng_regs_read(void *opaque, hwaddr addr, unsigned size)
case R_INTR_TEST:
case R_ALERT_TEST:
case R_CMD_REQ:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
__func__, (uint32_t)addr, REG_NAME(reg));
val32 = 0;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
(uint32_t)addr);
val32 = 0;
break;
}
Expand Down Expand Up @@ -1925,14 +1924,13 @@ static void ot_csrng_regs_write(void *opaque, hwaddr addr, uint64_t val64,
case R_INT_STATE_VAL:
case R_ERR_CODE:
case R_MAIN_SM_STATE:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
__func__, (uint32_t)addr, REG_NAME(reg));
break;
default:
// JW: handle new registers.
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
(uint32_t)addr);
break;
}
};
Expand Down
38 changes: 16 additions & 22 deletions hw/opentitan/ot_dma.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1177,15 +1177,13 @@ static uint64_t ot_dma_regs_read(void *opaque, hwaddr addr, unsigned size)
break;
case R_INTR_TEST:
case R_ALERT_TEST:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
__func__, s->ot_id, addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%03x (%s)\n",
__func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
val32 = 0;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
s->ot_id, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
s->ot_id, (uint32_t)addr);
val32 = 0;
break;
}
Expand Down Expand Up @@ -1260,19 +1258,17 @@ static void ot_dma_regs_write(void *opaque, hwaddr addr, uint64_t val64,
case R_DEST_ADDR_LIMIT_LO ... R_DEST_ADDR_LIMIT_HI:
case R_DEST_ADDR_THRESHOLD_LO ... R_DEST_ADDR_THRESHOLD_HI:
qemu_log_mask(LOG_UNIMP,
"%s: %s: Limit reg 0x%02" HWADDR_PRIx " (%s) is not "
"supported\n",
__func__, s->ot_id, addr, REG_NAME(reg));
"%s: %s: Limit reg 0x%03x (%s) is not supported\n",
__func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
s->regs[reg] = val32;
break;
case R_ENABLED_MEMORY_RANGE_BASE:
case R_ENABLED_MEMORY_RANGE_LIMIT:
if (!ot_dma_is_range_locked(s)) {
s->regs[reg] = val32;
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: %s: 0x%02" HWADDR_PRIx " (%s) is locked\n",
__func__, s->ot_id, addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: 0x%03x (%s) is locked\n",
__func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
/* not sure what to do here, should we set an error? */
}
break;
Expand All @@ -1282,9 +1278,9 @@ static void ot_dma_regs_write(void *opaque, hwaddr addr, uint64_t val64,
break;
case R_HANDSHAKE_INTR:
qemu_log_mask(LOG_UNIMP,
"%s: %s: Handshake reg 0x%02" HWADDR_PRIx " (%s) is not "
"%s: %s: Handshake reg 0x%03x (%s) is not "
"supported\n",
__func__, s->ot_id, addr, REG_NAME(reg));
__func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
val32 &= R_HANDSHAKE_INTR_ENABLE_MASK;
s->regs[reg] = val32;
break;
Expand All @@ -1297,9 +1293,8 @@ static void ot_dma_regs_write(void *opaque, hwaddr addr, uint64_t val64,
val32 &= R_RANGE_VALID_VALID_MASK;
s->regs[reg] = val32;
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: %s: 0x%02" HWADDR_PRIx " (%s) is locked\n",
__func__, s->ot_id, addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: 0x%03x (%s) is locked\n",
__func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
}
break;
case R_RANGE_REGWEN:
Expand Down Expand Up @@ -1353,13 +1348,12 @@ static void ot_dma_regs_write(void *opaque, hwaddr addr, uint64_t val64,
case R_CFG_REGWEN:
case R_ERROR_CODE:
case R_SHA2_DIGEST_0 ... R_SHA2_DIGEST_15:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
__func__, s->ot_id, addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%03x (%s)\n",
__func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%" HWADDR_PRIx "\n",
__func__, s->ot_id, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%03x\n", __func__,
s->ot_id, (uint32_t)addr);
break;
}
};
Expand Down
18 changes: 8 additions & 10 deletions hw/opentitan/ot_edn.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1351,14 +1351,13 @@ static uint64_t ot_edn_regs_read(void *opaque, hwaddr addr, unsigned size)
case R_SW_CMD_REQ:
case R_RESEED_CMD:
case R_GENERATE_CMD:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
__func__, (uint32_t)addr, REG_NAME(reg));
val32 = 0;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
(uint32_t)addr);
val32 = 0;
break;
}
Expand Down Expand Up @@ -1466,13 +1465,12 @@ static void ot_edn_regs_write(void *opaque, hwaddr addr, uint64_t val64,
case R_SW_CMD_STS:
case R_ERR_CODE:
case R_MAIN_SM_STATE:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
addr, REG_NAME(reg));
qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
__func__, (uint32_t)addr, REG_NAME(reg));
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, addr);
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
(uint32_t)addr);
break;
}
};
Expand Down
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