igs/pgm.cpp: one new set and another promoted to working#14981
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Osso13 wants to merge 3 commits intomamedev:masterfrom
Open
igs/pgm.cpp: one new set and another promoted to working#14981Osso13 wants to merge 3 commits intomamedev:masterfrom
Osso13 wants to merge 3 commits intomamedev:masterfrom
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------------------ Zhan Shen Chuan Shuo 2 Tebie Ban (bootleg of Knights of Valour Super Heroes Plus, V201CN, May 17 2010 10:43:09) [eziochiu, Mr.Qin] Clones promoted to working -------------------------- Gaishi Yingxiong Jiaqiang Ban (bootleg of Knights of Valour Super Heroes Plus, V302CN, Dec 29 2010 16:31:32) [eziochiu, Mr.Qin]
cuavas
reviewed
Feb 18, 2026
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| uint32_t lpc2132_vic_device::read_vector_address() | ||
| { | ||
| uint32_t irq_pending = m_vic_int_enable & m_vic_raw_intr & ~m_vic_int_select; | ||
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| if (irq_pending == 0) | ||
| { | ||
| m_vic_vect_addr_cur = m_vic_def_vect_addr; | ||
| return m_vic_vect_addr_cur; | ||
| } | ||
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| // Iterate through 16 vector slots to find matching interrupt | ||
| for (int i = 0; i < 16; i++) | ||
| { | ||
| if (m_vic_vect_cntl[i] & 0x20) // Check enable bit | ||
| { | ||
| uint32_t irq_source = m_vic_vect_cntl[i] & 0x1f; | ||
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| if (irq_pending & (1 << irq_source)) | ||
| { | ||
| m_vic_vect_addr_cur = m_vic_vect_addr[i]; | ||
| return m_vic_vect_addr_cur; | ||
| } | ||
| } | ||
| } | ||
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| // No matching vectored interrupt, return default address | ||
| m_vic_vect_addr_cur = m_vic_def_vect_addr; | ||
| return m_vic_vect_addr_cur; | ||
| } |
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Should this have side effect checks?
scripts/src/machine.lua
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| --------------------------------------------------- | ||
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| -- | ||
| --@src/devices/machine/lpc2132_vic.h,MACHINES["LPC2132_VIC"] = true | ||
| --------------------------------------------------- | ||
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| if (MACHINES["LPC2132_VIC"]~=null) then | ||
| files { | ||
| MAME_DIR .. "src/devices/machine/lpc2132_vic.cpp", | ||
| MAME_DIR .. "src/devices/machine/lpc2132_vic.h", | ||
| } | ||
| end |
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Can you try to find a sensible place for this and not add a random number of blank lines at the end of the file?
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| for (int i = 0; i < 0x400000; i+=2) { | ||
| src[i + 0x000001] = src[i + 0x800000]; | ||
| src[i + 0x400001] = src[i + 0xc00000]; | ||
| } |
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This is an Allman-formatted file, isn’t it?
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| for (int i = 0; i < 0x400000 / 2; i++) | ||
| { | ||
| int j = bitswap<24>((i & 0x7ffff) | ((((i >> 19) + 1) & 3) << 19), 23, 22, 21, 20, 19, 18, 16, 1, 3, 5, 7, 9, 11, 13, 15, 17, 14, 12, 10, 8, 6, 4, 0, 2); |
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Can’t you simplify (i & 0x7ffff) | ((((i >> 19) + 1) & 3) to ((i + 0x80000) & 0x1fffff)
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| for (int i = 0; i < 0x400000 / 2; i++) | ||
| { | ||
| int j = bitswap<24>((i & 0x7ffff) | ((((i >> 19) + 1) & 3) << 19), 23, 22, 21, 20, 19, 2, 1, 18, 17, 16, 15, 14, 13, 12, 11, 10, 0, 3, 4, 5, 6, 7, 8, 9); |
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Same here - the manipulation looks overly complicated.
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| void pgm_arm_type1_state::kovgsyx_asic27a_write_word(offs_t offset, u16 data) | ||
| { | ||
| machine().scheduler().synchronize(); | ||
| if (offset & 1) | ||
| { | ||
| m_kovgsyx_highlatch_68k_w = data; | ||
| m_lpc2132_vic->set_irq(16, ASSERT_LINE); | ||
| m_kovgsyx_lowlatch_arm_w = 0; | ||
| } | ||
| else | ||
| { | ||
| m_kovgsyx_lowlatch_68k_w = data; | ||
| m_kovgsyx_highlatch_arm_w = 0; | ||
| } | ||
| } |
Member
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It’s no use putting a machine().scheduler().synchronize(); there and then doing whatever it is immediately – you’ll still have the effect visible immediately. You need to pass a callback to synchronize to make the effects visible after the CPUs have caught up with each other.
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| u16 pgm_arm_type1_state::kovgsyx_asic27a_read_word(offs_t offset) | ||
| { | ||
| if (!machine().side_effects_disabled()) | ||
| machine().scheduler().synchronize(); | ||
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| if (offset & 1) | ||
| return m_kovgsyx_highlatch_arm_w; | ||
| else | ||
| return m_kovgsyx_lowlatch_arm_w; | ||
| } |
Member
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Same here – the machine().scheduler().synchronize(); isn’t doing what you want. It’s effectively going to happen after the read, so it’s no use.
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| u32 pgm_arm_type1_state::kovgsyx_lpc2132_read_long(offs_t offset) | ||
| { | ||
| if ((offset & 0x3fffc0) == 0x7f000) { | ||
| switch (offset & 0x3f) | ||
| { | ||
| case 0x20: | ||
| return m_kovgsyx_pll_enabled; | ||
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| case 0x21: | ||
| return m_kovgsyx_pll_config; | ||
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| case 0x22: | ||
| { | ||
| u32 status = 0; | ||
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| if (m_kovgsyx_pll_enabled) { | ||
| m_kovgsyx_pll_lock_timer++; | ||
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| if (m_kovgsyx_pll_lock_timer > 10) { | ||
| status |= 0x0400; | ||
| } | ||
| } | ||
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| status |= (m_kovgsyx_pll_enabled & 0x03) << 8; | ||
| status |= (m_kovgsyx_pll_config & 0x1f); | ||
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| return status; | ||
| } | ||
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| case 0x23: | ||
| return 0; | ||
| } | ||
| } |
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More mixed Allman and K&R in this function. Also in the one below.
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| m_kovgsyx_highlatch_arm_w = 0; | ||
| m_kovgsyx_lowlatch_arm_w = 0; | ||
| m_kovgsyx_highlatch_68k_w = 0; | ||
| m_kovgsyx_lowlatch_68k_w = 0; | ||
| m_kovgsyx_pll_lock_timer = 0; | ||
| m_kovgsyx_pll_enabled = 0; | ||
| m_kovgsyx_pll_config = 0; | ||
| m_kovgsyx_i2c1sclh = 0; | ||
| m_kovgsyx_i2c1conset = 0; | ||
| m_kovgsyx_i2c1dat = 0; | ||
| m_kovgsyx_i2c1_status = 0x08; | ||
| m_kovgsyx_handshake_done = 0; | ||
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| save_item(NAME(m_kovgsyx_highlatch_arm_w)); | ||
| save_item(NAME(m_kovgsyx_lowlatch_arm_w)); | ||
| save_item(NAME(m_kovgsyx_highlatch_68k_w)); | ||
| save_item(NAME(m_kovgsyx_lowlatch_68k_w)); | ||
| save_item(NAME(m_kovgsyx_pll_lock_timer)); | ||
| save_item(NAME(m_kovgsyx_pll_enabled)); | ||
| save_item(NAME(m_kovgsyx_pll_config)); | ||
| save_item(NAME(m_kovgsyx_i2c1sclh)); | ||
| save_item(NAME(m_kovgsyx_i2c1conset)); | ||
| save_item(NAME(m_kovgsyx_i2c1dat)); | ||
| save_item(NAME(m_kovgsyx_i2c1_status)); | ||
| save_item(NAME(m_kovgsyx_handshake_done)); |
Member
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You’ve got multiple copy/pastes of this. Are you sure it shouldn’t be in a derived class?
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New working clones
Zhan Shen Chuan Shuo 2 Tebie Ban (bootleg of Knights of Valour Super Heroes Plus, V201CN, May 17 2010 10:43:09) [eziochiu, Mr.Qin]
Clones promoted to working
Gaishi Yingxiong Jiaqiang Ban (bootleg of Knights of Valour Super Heroes Plus, V302CN, Dec 29 2010 16:31:32) [eziochiu, Mr.Qin]