openvmm/pcie: introduce and consume pcie root complex and port emulators

Cargo.lock

@@ -3059,6 +3059,7 @@ dependencies = [
  "pal_async",
  "pci_bus",
  "pci_core",
+ "pcie",
  "range_map_vec",
  "scsi_core",
  "scsidisk",
@@ -5506,6 +5507,21 @@ dependencies = [
  "vmcore",
 ]
 
+[[package]]
+name = "pcie"
+version = "0.0.0"
+dependencies = [
+ "chipset_device",
+ "inspect",
+ "pal_async",
+ "pci_bus",
+ "pci_core",
+ "tracelimit",
+ "tracing",
+ "vmcore",
+ "zerocopy 0.8.25",
+]
+
 [[package]]
 name = "pem-rfc7468"
 version = "0.7.0"

Cargo.toml

@@ -256,6 +256,7 @@ vmswitch = { path = "vm/devices/net/vmswitch" }
 pci_bus = { path = "vm/devices/pci/pci_bus" }
 pci_core = { path = "vm/devices/pci/pci_core" }
 pci_resources = { path = "vm/devices/pci/pci_resources" }
+pcie = { path = "vm/devices/pci/pcie" }
 vpci = { path = "vm/devices/pci/vpci" }
 vpci_client = { path = "vm/devices/pci/vpci_client" }
 vpci_protocol = { path = "vm/devices/pci/vpci_protocol" }

openvmm/hvlite_core/Cargo.toml

@@ -62,6 +62,7 @@ input_core.workspace = true
 missing_dev.workspace = true
 pci_bus.workspace = true
 pci_core.workspace = true
+pcie.workspace = true
 scsi_core.workspace = true
 scsidisk.workspace = true
 serial_16550_resources.workspace = true

openvmm/hvlite_core/src/worker/dispatch.rs

@@ -75,6 +75,8 @@ use pal_async::task::Spawn;
 use pal_async::task::Task;
 use pci_core::PciInterruptPin;
 use pci_core::msi::MsiInterruptSet;
+use pcie::root::GenericPcieRootComplex;
+use pcie::root::GenericPcieRootPortDefinition;
 use scsi_core::ResolveScsiDeviceHandleParams;
 use scsidisk::SimpleScsiDisk;
 use scsidisk::atapi_scsi::AtapiScsiDisk;
@@ -1749,11 +1751,31 @@ impl InitializedVm {
             let mut high_mmio_address = cfg.memory.mmio_gaps[1].end();
 
             for rc in cfg.pcie_root_complexes {
-                let bus_count = (rc.end_bus as u16) - (rc.start_bus as u16) + 1;
-                let ecam_size = (bus_count as u64) * 256 * 4096;
-                let low_mmio_size = rc.low_mmio_size as u64;
+                let device_name = format!("pcie-root:{}", rc.name);
+                let root_complex =
+                    chipset_builder
+                        .arc_mutex_device(device_name)
+                        .add(|services| {
+                            let root_port_definitions = rc
+                                .ports
+                                .into_iter()
+                                .map(|rp_cfg| GenericPcieRootPortDefinition {
+                                    name: rp_cfg.name.into(),
+                                })
+                                .collect();
 
-                let host_bridge = PcieHostBridge {
+                            GenericPcieRootComplex::new(
+                                &mut services.register_mmio(),
+                                rc.start_bus,
+                                rc.end_bus,
+                                ecam_address,
+                                root_port_definitions,
+                            )
+                        })?;
+
+                let ecam_size = root_complex.lock().ecam_size();
+                let low_mmio_size = rc.low_mmio_size as u64;
+                pcie_host_bridges.push(PcieHostBridge {
                     index: rc.index,
                     segment: rc.segment,
                     start_bus: rc.start_bus,
@@ -1763,9 +1785,7 @@ impl InitializedVm {
                     high_mmio: MemoryRange::new(
                         high_mmio_address..high_mmio_address + rc.high_mmio_size,
                     ),
-                };
-
-                pcie_host_bridges.push(host_bridge);
+                });
 
                 ecam_address += ecam_size;
                 low_mmio_address -= low_mmio_size;

vm/devices/pci/pcie/Cargo.toml

@@ -0,0 +1,21 @@
+# Copyright (c) Microsoft Corporation.
+# Licensed under the MIT License.
+
+[package]
+name = "pcie"
+rust-version.workspace = true
+edition.workspace = true
+
+[dependencies]
+chipset_device.workspace = true
+inspect.workspace = true
+pal_async.workspace = true
+pci_bus.workspace = true
+pci_core.workspace = true
+tracing.workspace = true
+tracelimit.workspace = true
+vmcore.workspace = true
+zerocopy.workspace = true
+
+[lints]
+workspace = true

vm/devices/pci/pcie/src/lib.rs

@@ -0,0 +1,25 @@
+// Copyright (c) Microsoft Corporation.
+// Licensed under the MIT License.
+
+//! PCI Express definitions and emulators.
+
+#![forbid(unsafe_code)]
+
+pub mod root;
+
+#[cfg(test)]
+mod test_helpers;
+
+const PAGE_SIZE: usize = 4096;
+const PAGE_SIZE64: u64 = 4096;
+const PAGE_OFFSET_MASK: u64 = PAGE_SIZE64 - 1;
+const PAGE_SHIFT: u32 = PAGE_SIZE.trailing_zeros();
+
+const VENDOR_ID: u16 = 0x1414;
+const ROOT_PORT_DEVICE_ID: u16 = 0xF111;
+
+const MAX_FUNCTIONS_PER_BUS: usize = 256;
+
+const BDF_BUS_SHIFT: u16 = 8;
+const BDF_DEVICE_SHIFT: u16 = 3;
+const BDF_DEVICE_FUNCTION_MASK: u16 = 0x00FF;