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Releases: mirseo/JSilicon

JSilicon v0.2 First Tapeout-Ready Version

07 Oct 10:11
@mirseo mirseo
JSilicon-v0.2
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JSilicon v0.2 Overview

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JSilicon is an 8-bit CPU/ALU core designed and implemented from scratch during my mandatory military service in South Korea (2025). This project serves as a proof-of-concept, showing that a complete silicon design is achievable even in highly constrained environments.

Version 0.2 expands on the original manual ALU functionality by adding a CPU mode that automatically executes pre-programmed instructions. To enable this, key CPU components such as a Program Counter (PC), an instruction decoder, and a register file have been integrated.

Inspired by JavaScript's simplicity and the philosophy of accessible silicon design, the JSilicon series aims to develop an ASIC that can natively power a JS runtime.

  • PC (Program Counter & ROM) - Stores a 16x8-bit instruction set in its internal ROM and sequentially fetches them in CPU mode.

  • Decoder - Parses instructions from PC and generates control signals for other components.

  • REG (Register File) - Contains two 8-bit general-purpose registers (R0, R1) that serve as the CPU's workspace.

  • ALU (Arithmetic Logic Unit) - Performs eight fundamental arithmetic and logic operations, including addition, subtraction, and multiplication.

  • SWITCH - A multiplexer that selects the data path based on the Mode pin, switching between external manual inputs and the internal CPU core.

  • FSM (Finite State Machine) - Acts as the central controller, managing the timing for ALU execution and UART transmission.

  • UART_TX - Serializes the computation result and transmits it to an external device like a PC or MCU.

Please consult the complete datasheet PDF for detailed technical specifications, pin assignments, and testing procedures.

JSilicon_ASIC_v0.2.pdf

Explore

Explore the physical layout of JSilicon v0.2 in full 3D.
This interactive viewer lets you navigate through the final GDSII structure of the chip — from standard cells to routing layers — exactly as it will appear on silicon.

View JSilicon v0.2 GDS Layout in 3D

  • Clock : Design expects a 12Mhz input clock. (TinyTapeout standard)
  • Logic Levels : All I/O pins use 3.3 V CMOS Logic
  • Bidirectional Pins : The uio pins are used for both input and output. As inputs, uio[7:5] select the manual opcode and uio[4] selects the operation mode. As an output, only uio[0] is actively driven for UART TX. The remaining pins (uio[3:1]) are unused.
  • And All Test pass :)

License

This project is licensed under the MIT License.

Author Message

Hello, I'm JunHyeok Seo, currently serving my mandatory military service here in the Republic of Korea.

The reason I created the JSilicon project was to prove that even time spent in the military can be meaningful. And I will see it through. Even when there seems to be no path forward, I will find a way, just as I always have.

You can create something like this even with a low-spec computer or on a device that lags and crashes when you open just one or two browser tabs. Do not give up. Just as I managed to build this chip, you can achieve it too.

Copyright 2025. JunHyeok Seo (mirseo). All rights reserved.

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