Use one struct for R4300 registers on all architectures

[Nebuleon]

The New Dynarec/ARM redefines global variables in its own memory block in order to bring a lot of them together in memory for easy indexing. This PR does the same for all other R4300 cores on all architectures by moving a lot of often-used global variables from many files into one struct in r4300.c:

reg[32], hi, lo, g_cp0_regs[32], FCR0, FCR31, llbit, reg_cop1_simple[32], reg_cop1_double[32], reg_cop1_fgr_64[32], delay_slot, next_interupt, address, rdword, cpu_byte, cpu_hword, cpu_word, cpu_dword => g_state

The compiler is then allowed to reference every member of that structure with offsets from a single address, which is faster on ARM and MIPS (and may or may not be faster on x86 due to processor microarchitecture changes) when emitting position-independent code.

In addition, I have aligned the new structure to 4 KiB in order to induce only 1 TLB miss for accessing it.

The new structure is hidden and recreated in the New Dynarec/ARM as usual, but the number of recreated variables is greatly reduced.

I expect the performance to increase in these cores:

• Pure Interpreter: 2%..10% faster, due to fewer reloads of global variable addresses, increased cache locality and reduced TLB misses; this depends on a game's use of multiplier unit instructions, MFC0, MTC0, [D]MFC1, [D]MTC1, floating-point width conversion instructions and memory access instructions, which accessed more than one global variable (and now access the members of the structure).
• Cached Interpreter: <2% faster, due to increased cache locality and reduced TLB misses. It loads operand pointers from a struct precomp_instr, so after compilation, there are no reloads of global variable addresses.
• Hacktarux JIT/x86, x86-64: <2% faster, due to increased cache locality and reduced TLB misses. Better code could be generated to take advantage of the new structure, but I didn't change anything there.

A possibly undesirable aspect of this change is that the Coprocessor 0-related variables are no longer in cp0.c, the FPU is no longer in cp1.c, and the global variables used as parameters to the memory accessor functions are no longer in memory.c.

Commit 3c9a3fc will definitely not build on ARM, and bbe2a26 should build, but I don't know if it works properly because I don't have an ARM device to test with.

[Narann]

Interesting, I would wait for others to comment before merge such PR. Thanks for the hard work!

[Nebuleon]

Of course; I even had a build failure, so it's possible that there are more errors lurking. Travis didn't get notified about commit 7bd0078 either, apparently.