pipe_id_ex.sv

// Pipeline register: ID/EX (Stage 2 → Stage 3)
module pipe_id_ex
  #(
    parameter BITS = 32,
    parameter REG_ADDR_BITS = 5,
    parameter SHIFT_BITS = 5,
    parameter OP_BITS = 4
  )
  (
    input  logic                      clk,
    input  logic                      rst_,
    input  logic                      stall_pipe,  // Stall signal for bubble insertion
    
    // Stage 2 inputs
    input  logic [BITS-1:0]           r1_data,
    input  logic [BITS-1:0]           r2_data,
    input  logic [BITS-1:0]           sign_ext_imm,
    input  logic [REG_ADDR_BITS-1:0]  r1_addr,
    input  logic [REG_ADDR_BITS-1:0]  r2_addr,
    input  logic [REG_ADDR_BITS-1:0]  waddr,
    input  logic [SHIFT_BITS-1:0]     shamt,
    input  logic [OP_BITS-1:0]        alu_op,
    input  logic                      alu_imm,
    input  logic                      rw_,
    input  logic                      mem_rw_,
    input  logic                      sel_mem,
    input  logic [3:0]                byte_en,
    input  logic                      halt,
    input  logic                      atomic,
    input  logic                      load_link_,
    input  logic                      check_link,
    
    // Stage 3 outputs
    output logic [BITS-1:0]           r1_data_s3,
    output logic [BITS-1:0]           r2_data_s3,
    output logic [BITS-1:0]           sign_ext_imm_s3,
    output logic [REG_ADDR_BITS-1:0]  r1_addr_s3,
    output logic [REG_ADDR_BITS-1:0]  r2_addr_s3,
    output logic [REG_ADDR_BITS-1:0]  waddr_s3,
    output logic [SHIFT_BITS-1:0]     shamt_s3,
    output logic [OP_BITS-1:0]        alu_op_s3,
    output logic                      alu_imm_s3,
    output logic                      rw_s3,
    output logic                      mem_rw_s3,
    output logic                      sel_mem_s3,
    output logic [3:0]                byte_en_s3,
    output logic                      halt_s3,
    output logic                      atomic_s3,
    output logic                      load_link_s3,
    output logic                      check_link_s3
  );

  always_ff @(posedge clk or negedge rst_) begin
    if (!rst_) begin
      // Reset: all control signals inactive
      r1_data_s3      <= {BITS{1'b0}};
      r2_data_s3      <= {BITS{1'b0}};
      sign_ext_imm_s3 <= {BITS{1'b0}};
      r1_addr_s3      <= {REG_ADDR_BITS{1'b0}};
      r2_addr_s3      <= {REG_ADDR_BITS{1'b0}};
      waddr_s3        <= {REG_ADDR_BITS{1'b0}};
      shamt_s3        <= {SHIFT_BITS{1'b0}};
      alu_op_s3       <= {OP_BITS{1'b0}};
      alu_imm_s3      <= 1'b0;
      rw_s3           <= 1'b1;  // No write
      mem_rw_s3       <= 1'b1;  // No write
      sel_mem_s3      <= 1'b0;
      byte_en_s3      <= 4'hF;
      halt_s3         <= 1'b0;
      atomic_s3       <= 1'b0;
      load_link_s3    <= 1'b0;
      check_link_s3   <= 1'b0;
    end else if (stall_pipe) begin
      // Stall: insert bubble (NOP) - set control signals to inactive
      rw_s3           <= 1'b1;  // No register write
      mem_rw_s3       <= 1'b1;  // No memory write
      atomic_s3       <= 1'b0;  // Not atomic
      check_link_s3   <= 1'b0;  // Not checking link
      load_link_s3    <= 1'b0;  // Not loading link
      sel_mem_s3      <= 1'b0;  // Not selecting memory
      halt_s3         <= 1'b0;  // Not halting
      // Data signals can keep their values (won't be used)
    end else begin
      // Normal operation: pass through all signals
      r1_data_s3      <= r1_data;
      r2_data_s3      <= r2_data;
      sign_ext_imm_s3 <= sign_ext_imm;
      r1_addr_s3      <= r1_addr;
      r2_addr_s3      <= r2_addr;
      waddr_s3        <= waddr;
      shamt_s3        <= shamt;
      alu_op_s3       <= alu_op;
      alu_imm_s3      <= alu_imm;
      rw_s3           <= rw_;
      mem_rw_s3       <= mem_rw_;
      sel_mem_s3      <= sel_mem;
      byte_en_s3      <= byte_en;
      halt_s3         <= halt;
      atomic_s3       <= atomic;
      load_link_s3    <= load_link_;
      check_link_s3   <= check_link;
    end
  end

endmodule